Overview
1119
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.1.2.1 Multi-buffer Mode
Multi-buffer Mode is an extension to the SPI. In multi-buffer mode, many extended features are
configurable:
•
Number of buffers for each peripheral (or data source/destination, up to 128 buffers supported) or
group (up to 8 groupings)
•
Triggers for each groups, trigger types, trigger sources for individual groups (14 external trigger
sources and 1 internal trigger source supported)
•
Memory fault detection via an internal parity circuit
•
Number of DMA-controlled buffers and number of DMA request channels (up to 8 for each of transmit
and receive)
•
Number of DMA transfers for each buffer (up to 65536 words for up to 8 buffers)
•
Uninterrupted DMA buffer transfer (NOBREAK buffer)
24.1.2.2 Compatibility Mode
Compatibility Mode of the MibSPI makes it behave exactly like a standard platform SPI module and
ensures full compatibility with other SPIs. All features in compatibility mode of the MibSPI are directly
applicable to a SPI. Multi-buffer Mode features are not available in Compatibility Mode.
NOTE:
The SPIDAT0 register is not accessible in the multi-buffer mode of MibSPI. It is only
accessible in compatibility mode.
24.1.3 Transmission Lock (Multi-Buffer Mode Master Only)
Some slave devices require transmission of a command followed by data. In this case the SPI transaction
should not be interrupted by another group transfer. The LOCK bit within each buffer allows a consecutive
transfer to happen without being interrupted by another higher-priority group transfer.
24.2 Operating Modes
The SPI can be configured via software to operate as either a master or a slave. The MASTER bit
(SPIGCR1[0]) selects the configuration of the SPISIMO and SPISOMI pins. CLKMOD bit (SPIGCR1[1])
determines whether an internal or external clock source will be used.
The slave chip select (SPICS) pins are used when communicating with multiple slave devices or, with a
single slave, to delimit messages containing a leading register address. When a write occurs to SPIDAT1
in master mode, the SPICS pins are automatically driven to select the specified slave.
Handshaking mechanism, provided by the SPIENA pin, enables a slave SPI to delay the generation of the
clock signal supplied by the master if it is not prepared for the next exchange of data.
NOTE:
If in the slave mode of operation and configured in either 3-pin or 4-pin (without SPIENA)
modes, there must be a minimum of 8 VCLK cycles of delay between the last SPICLK and
the start of the SPICLK for the next buffer transmit. In general, this equates to a
VCLK/SPICLK ratio of
≤
16 requiring a minimum of 1 SPICLK delay between transmissions.
