Module Operation
411
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Error Signaling Module (ESM)
12.2 Module Operation
This device has 128 error channels, divided into 3 different error groups. Please refer to the device
datasheet for ESM channel assignment details.
The ESM module has error flags for each error channel. The error status registers ESMSR1, ESMSR4,
ESMSR2, ESMSR3 provide status information on a pending error of Group1 (Channel 0-31), Group1
(Channel 32-63), Group2, and Group3, respectively. The ESMEPSR register provides the current ERROR
status. The module also provides a status shadow register, ESMSSR2, which maintains the error flags of
Group2 until power-on reset (PORRST) is asserted. See
for details of their behavior during
power on reset and warm reset.
Once an error occurs, the ESM module will set the corresponding error flags. In addition, it can trigger an
interrupt, ERROR pin outputs low depending on the ESM settings. Once the ERROR pin outputs low, a
power on reset or a write of 5h to ESMEKR is required to release the ESM error pin back to normal state.
See
for details. The application can read the error status registers (ESMSR1, ESMSR4,
ESMSR2, and ESMSR3) to debug the error. If an RST is triggered or the error interrupt has been served,
the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared
by RST.
The user can also test the functionality of the ERROR pin by forcing an error. See
for
details.
12.2.1 Reset Behavior
Power on reset:
•
ERROR pin behavior
When PORRST is active, the ERROR pin is in a high impedance state (output drivers disabled).
•
Register behavior
After PORRST, all registers in ESM module will be re-initialized to the default value. All the error status
registers are cleared to zero.
Warm reset (RST):
•
ERROR pin behavior
During RST, the ERROR pin is in “output active” state with pull-down disabled. The ERROR pin
remains unchanged after RST.
•
Register behavior
After RST, ESMSR1, ESMSR4, ESMSSR2, ESMSR3 and ESMEPSR register values remains un-
changed. Since RST does not clear the critical failure registers, the user can read those registers to
debug the failures after RST pin goes back to high.
After RST, if one of the flags in ESMSR1 and ESMSR4 is set, the interrupt service routine will be
called once the corresponding interrupt is enabled.
NOTE:
ESMSR2 is cleared after RST. The flag in ESMSR2 gets cleared when reading the
appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the
ESMSR1, ESMSR4, and the shadow register ESMSSR2. Reading ESMIOFFLR will also not
clear the ESMSR1 and ESMSR4.
