ADC Control Registers
764
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Analog To Digital Converter (ADC) Module
19.11.37 ADC Event Group Results' FIFO Register (ADEVBUFFER)
ADC Event Group Results' FIFO Register (ADEVBUFFER) is shown in
and
and described in
. As shown, the format of the data read from the ADEVBUFFER locations is
different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-58. 12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)
[offset = 90h-AFh]
31
30
21
20
16
EV_EMPTY
Reserved
EV_CHID
R-1
R-0
R-0
15
12
11
0
Reserved
EV_DR
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset; -U = value after reset is unknown
Figure 19-59. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER)
[offset = 90h-AFh]
31
16
Reserved
R-0
15
14
10
9
0
EV_EMPTY
EV_CHID
EV_DR
R-1
R-0
R-U
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset; -U = value after reset is unknown
Table 19-42. ADC Event Group Results' FIFO Register (ADEVBUFFER) Field Descriptions
Field
Value
Description
Reserved
0
Reads return zeros, writes have no effect.
EV_EMPTY
Event Group FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading
the Event Group conversion results.
Any operation mode read:
0
The data in the EV_DR field of this buffer is valid.
1
The data in the EV_DR field of this buffer is not valid and there are no valid data in the Event Group results
memory.
EV_CHID
Event Group Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Event Group conversion results.
Any operation mode read:
0
The conversion result in the EV_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Event Group operating mode control register (ADEVMODECR).
1h-1Fh
The conversion result in the EV_DR field of this buffer is from the ADC input channel number denoted by
the EV_CHID field.
EV_DR
Event Group Digital Conversion Result.
The Event Group results’ FIFO location is aliased eight times, so that any word-aligned read from the
address range 0x90 to 0xAF results in one conversion result to be read from the Event Group results’
memory. This allows the ARM LDMIA instruction to read out up to 8 conversion results from the Event
Group results’ memory with just one instruction.