USB Device Controller
1606
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
Autodecoded control read and control write transfers are sets of transactions that occur on endpoint 0 that
have specific USB protocol meaning and are handled automatically by the USB device controller block
without any intervention by the CPU. The USB device controller block handles all handshaking
automatically and without regard to the endpoint 0 control bits that affect normal (non-control transfer)
transaction handshaking. No interrupt is asserted to the CPU during autodecoded control transfers.
If no USB1.1 specification defined request is associated with the data of the setup phase, request is
stalled by the core and the CPU is not informed of its occurrence (autodecoded).
When a setup token is identified, the USB decode module must monitor the setup stage data packet,
decode it, and determine whether it is an autodecoded or a non-autodecoded transfer and a control read
or a control write. If it is a valid non-autodecoded request, the setup FIFO is immediately cleared and
control of the FIFO is immediately taken away from the CPU (if the CPU had control of the FIFO). New
setup data are placed into the setup FIFO, and the setup interrupt flag is set (IRQ_SRC.setup).
In response to the setup interrupt, the CPU must select the setup FIFO by setting the
EP_NUM.SETUP_SEL bit. This clears the IRQ_SRC.SETUP flag. The CPU must then read 8 bytes from
the setup FIFO, clear the EP_NUM.SETUP_SEL bit, and confirm that IRQ_SRC.SETUP bit has not been
reset by a new setup transaction. If the IRQ_SRC.SETUP flag is asserted, the CPU must discard the
previously read data and handle the new setup packet as explained above. Thus the CPU never misses a
new occurring setup transaction (per USB 1.1 specification).
29.3.7.1 Autodecoded Control Write Transfers
For set address control write transfers, the USB address provided in the setup token is captured to the
USB module device address register. If new address is different from 0, the device moves into addressed
state (DEVSTAT.ADD set) if it was not already addressed.
For set and clear feature control writes, the appropriate feature information bit is set or cleared. When a
set or clear feature transfer occurs to set or clear the device remote wake-up feature, the
DEVSTAT.R_WK_OK bit is set or cleared, as appropriate. If a set or clear interface feature occurs, the
request is automatically stalled by the core because no feature is defined for interface (see the USB 1.1
specification).
Per the USB 1.1 specifications, a SET_ADDRESS request is effective after the status stage of the
request, even if the status stage does not end with an ACK handshake. SET/CLEAR_FEATURE requests
are effective after setup stage, even if no status stage occurs.
29.3.7.1.1 Autodecoded Control Write Transfer Handshaking
The USB device controller module automatically provides ACK handshaking for all transactions of all
stages of autodecoded control write transfers, except if a corrupted packet is received, which the USB
module ignores. The CTRL.SET_FIFO_EN and SYSCON2.STALL_CMD bits have no effect on
handshaking.
29.3.7.1.2 Autodecoded Control Write Transfer Error Conditions
If the token packet or the data packet of a setup stage transaction has an error (bad CRC, PID check, or
bit stuffing error), the USB block ignores the transaction. The USB block does not provide ACK
handshaking in this case.
