DEST[1]
SIZE[1]
ADDR[15] ADDR[11]
ADDR[7]
ADDR[3]
DATA[7]
DATA[3]
DEST[0]
ADDR[13]
ADDR[6]
ADDR[2]
DATA[2]
DATA[6]
DATA[5]
DATA[4]
ADDR[9]
ADDR[5]
ADDR[1]
DATA[1]
ADDR[4]
ADDR[0]
DATA[0]
SIZE[0]
ADDR[14] ADDR[10]
ADDR[12]
ADDR[8]
STAT[1]
STAT[0]
ADDR[17]
ADDR[16]
DMMCLK
DMMSYNC
DMMDATA[0]
DMMDATA[1]
DMMDATA[2]
DMMDATA[3]
Packet1
Packet2
Packet3
Packet4
Packet1
Packet2
Packet3
DMMCLK
DMMSYNC
DMMDATA
Module Operation
1664
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Data Modification Module (DMM)
30.2.2.1 Signal Description
DMMSYNC
This signal has to be provided by external hardware. It signals the start of a new
packet. It has to be active (high) for one full DMMCLK cycle, starting with the rising
edge of DMMCLK. If the DMMSYNC pulse is longer than a single DMMCLK cycle
and two falling edges of DMMCLK see a high pulse on DMMSYNC, the module will
treat the second DMMSYNC pulse as the start of a packet and will flag a
PACKET_ERR_INT (
DMMCLK
The clock is externally generated and can be suspended between two packets. For
this feature, CONTCLK must be set to 0 (
). If the clock is not stopped
between two packets, CONTCLK must be set to 1. Data will be latched on the
falling edge of the DMMCLK signal.
DMMENA
This signal is pulled high if no new data should be received via the data pins,
because of a potential overflow situation.
DMMDATA[15:0]
These pins receive the packet information transmitted by the external hardware.
Data is latched on the falling edge of DMMCLK.
shows an example of multiple packets received during trace mode, in noncontinuous clock
configuration.
Figure 30-4. Packet Sync Signal Example
shows an example of a 4-bit data port with 8-bit receive data (A5h) to be written into DEST1
(address 0001 2345h) on a trace mode packet.
Figure 30-5. Example Single Packet Transmission
30.2.3 Error Handling
The module will generate two different kind of errors. Once an error condition is recognized, an interrupt
will be generated if enabled.