Texas Instruments RM48 series, Technical Reference Manual

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Double Control Packet Configuration Memory
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1010 SPNU503C – March 2018
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High-End Timer Transfer Unit (HTU) Module
21.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT)
Figure 21-44. Initial N2HET Address and Control Register (HTU IHADDRCT)
31 24
Reserved
R-0
23 22 21 20 19 18 17 16
DIR SIZE ADDMH ADDMF TMBA TMBB
R/WP-X R/WP-X R/WP-X R/WP-X R/WP-X R/WP-X
15 13 12 2 1 0
Reserved IHADDR Reserved
R-0 R/WP-X R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; - n = value after reset; X = Unknown
Table 21-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reads return 0. Writes have no effect.
23 DIR Direction of Transfer
0 N2HET address is read and main memory address is written.
1 Main memory address is read and N2HET address is written.
22 SIZE Size of Transferred Data
0 32-bit transfer
1 64-bit transfer
64-bit transfer examples: If the N2HET address points to the N2HET instruction Control Field (CF), then
the CF and Data Field (DF) will be transferred. If the N2HET address points to the Program Field (PF),
then the PF and CF will be transferred.
21 ADDMH Addressing Mode N2HET Address. This bit determines the N2HET address index from one to the next
element of a frame.
0 Increment by 16 bytes.
Examples:
If the initial N2HET address points to data field of instruction (n). Then the N2HET fields to be
transferred by the elements of a frame are: data field of instruction (n), data field of instruction (n+1),
data field of instruction (n+2) and so on. If the initial N2HET address points to control field of instruction
(n), then the N2HET fields to be transferred by the elements of a frame are: control field of instruction
(n), control field of instruction (n+1), control field of instruction (n+2) and so on.
1 Increment by 8 bytes.
This mode is intended to be used together with the 64-bit transfer size to load short N2HET instruction
blocks into the N2HET RAM. So the sequence of transferred 64-bit elements could be: [PF and CF of
instruction (n)], [DF and RF of instruction (n)], [PF and CF of instruction (n+1)], [DF and RF of
instruction (n+1)] and so on.
20 ADDMF Addressing Mode Main Memory Address
0 Post-increment
Note: When post-increment is selected the HTU will automatically increment by 4 bytes for a 32-bit data
size and by 8 bytes for a 64-bit data size.
1 Constant
19-18 TMBA Transfer Mode for Buffer A
0 One-Shot buffer mode
1h Circular buffer mode
2h-3h Auto Switch mode
17-16 TMBB Transfer Mode for Buffer B
0 One-Shot buffer mode
1h Circular buffer mode
2h-3h Auto Switch mode