2
.
115
256
2
20
045
.
0
]
0
...
8
[
=
´
´
=
M U L M O D
2
20
045
.
0
2
256
]
0
...
8
[
´
=
´
=
=
D
N S
N V
M U LM O D
N F
2
NS
NV
NF
´
=
D
2
2 0
9 0
2
1 0 0
5
.
0
´
=
´
=
=
N V
N S
N F
N V
D e p th
Programming Example
391
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
4. Select the output divider OD so that the post-ODCLK frequency does not exceed the maximum
frequency of output divider R (device specific frequency). In this case, choose OD = 2 and R = 1.
5. Compute the divider value NV:
(18)
NV = 0.045
6. If it is important to maintain the same average frequency in modulation as in non-modulation, either NF
should be modified OR program the MULMOD bit field. The modulation fields create a multiplier offset
equal to:
(19)
If using MULMOD[8:0], then:
(20)
(21)
MULMOD will be set to 115.
7. Convert the PLL parameters into bit field values:
•
NR = 5, implies that REFCLKDIV[5:0] = 4
•
NS = 20, implies that SPRATE[8:0] = 19 = 0x13
•
NF = 90, implies that PLLMUL[15:0] = 0x5900
•
OD = 2, implies that ODPLL[2:0] = 1
•
R = 1, implies that PLLDIV[4:0] = 0
•
NV = 0.045, implies that SPR_AMOUNT[8:0] = 91 = 0x5B
•
MULMOD[8:0] = 115 = 0x73
8. Setting only these fields (that is, not BPOS, ROF, or ROS) yields:
PLLCTL1 = 0x00045900
PLLCTL2 = 0x04C7325B
When FM ENA is turned on, PLLCTL2 = 0x84C7325B
The Output CLK is centered in the range from 150MHz to 550MHz at 360MHz.
NF = 90 falls within the multiplier range from 1 to 256.
OD is selected so that post-ODCLK meets the device specification.
