Control Registers
1199
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 24-42. TG Control Registers (TGxCTRL) Field Descriptions (continued)
Bit
Field
Value
Description
19-16
TRIGSRCx
Trigger source. After reset, the trigger sources of all TGs are disabled.
0
Disabled
1h
EXT0
External trigger source 0. The actual source varies per device (for example, HET I/O
channel, event pin).
2h
EXT1
External trigger source 1. The actual source varies per device (for example, HET I/O
channel, event pin).
3h
EXT2
External trigger source 2. The actual source varies per device (for example, HET I/O
channel, event pin).
4h
EXT3
External trigger source 3. The actual source varies per device (for example, HET I/O
channel, event pin).
5h
EXT4
External trigger source 4. The actual source varies per device (for example, HET I/O
channel, event pin).
6h
EXT5
External trigger source 5. The actual source varies per device (for example, HET I/O
channel, event pin).
7h
EXT6
External trigger source 6. The actual source varies per device (for example, HET I/O
channel, event pin).
8h
EXT7
External trigger source 7. The actual source varies per device (for example, HET I/O
channel, event pin).
9h
EXT8
External trigger source 8. The actual source varies per device (for example, HET I/O
channel, event pin).
Ah
EXT9
External trigger source 9. The actual source varies per device (for example, HET I/O
channel, event pin).
Bh
EXT10
External trigger source 10. The actual source varies per device (for example, HET I/O
channel, event pin).
Ch
EXT11
External trigger source 11. The actual source varies per device (for example, HET I/O
channel, event pin).
Dh
EXT12
External trigger source 12. The actual source varies per device (for example, HET I/O
channel, event pin).
Eh
EXT13
External trigger source 13. The actual source varies per device (for example, HET I/O
channel, event pin).
Fh
TICK
Internal periodic event trigger. The tick counter can initiate periodic group transfers.
15
Reserved
0
Reads return 0. Writes have no effect.
14-8
PSTARTx
0-7Fh
TG start address. PSTARTx stores the start address of the corresponding TG. The corresponding
end address is inherently defined by the subsequent TG start address minus 1 (PENDx[TGx] =
PSTARTx[TGx+1]-1). PSTARTx is copied into PCURRENTx when:
• The TG is enabled
• The end of the TG is reached during a transfer
• A trigger event occurs while PRST is set to 1
7
Reserved
0
Reads return 0. Writes have no effect.
6-0
PCURRENTx
0-7Fh
Pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127) of
the buffer that corresponds to this TG. If the TG switches from active-transfer mode to suspend-to-
wait mode, PCURRENTx contains the address of the currently suspended word. After the TG
resumes from suspend-to-wait mode, the next buffer will be transferred; that is, no buffer data is
transferred because of suspend-to-wait mode.
NOTE:
Register bits vary by device
TG0 has the highest priority and TG15 has the lowest priority. Under the following conditions,
a lower-priority TG cannot be interrupted by a higher-priority TG:
1. When there is a CSHOLD or LOCK buffer, until the completion of the next buffer
transfer that is a non-CSHOLD or non-LOCK buffer.
2. An entire sequence of words transferred for a NOBRK DMA buffer.
3. Once the last word in a TG is pre-fetched.
