15 14 13 12 11 10 9 8
7
6
5 4 3
2
1
SIMO[7:0]
SOMI[7:0]
SPI Shift register
0
S
IM
O
7
S
IM
O
6
S
IM
O
5
S
IM
O
4
S
IM
O
3
S
IM
O
2
S
IM
O
1
S
IM
O
0
MULTIPLEXER
Parallel mode
S
O
M
I7
S
O
M
I6
S
O
M
I5
S
O
M
I4
S
O
M
I3
S
O
M
I2
S
O
M
I1
S
O
M
I0
DEMULTIPLEXER
15 14 13 12 11 10 9 8
7
6
5 4
3
2 1
SIMO[7:0]
SOMI[7:0]
SPI Shift register
S
IM
O
7
S
IM
O
6
S
IM
O
5
S
IM
O
4
S
IM
O
3
S
IM
O
2
S
IM
O
1
S
IM
O
0
MULTIPLEXER
Parallel mode
0
S
O
M
I7
S
O
M
I6
S
O
M
I5
S
O
M
I4
S
O
M
I3
S
O
M
I2
S
O
M
I1
S
O
M
I0
DEMULTIPLEXER
Operating Modes
1133
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Parallel mode can be programmed using the PMODEx bits of SPIPMCTRL register. See
for details about this register.
After reset the parallel mode selection bits are cleared (single SIMO/SOMI lines).
24.2.15.1 Parallel Mode Block Diagram
and
show the parallel connections to the SPI shift register.
Figure 24-14. Block Diagram Shift Register, MSB First
Figure 24-15. Block Diagram Shift Register, LSB First
