3µs
[2 x (13 x 9µs - 3µs)]
----------------------------------------------------------
min(TSeg1, TSeg2)
[2 x (13 x bit_time - TSeg2)]
-----------------------------------------------------------------------
0.1µs
[2 x (13 x 1µs - 0.1µs)]
----------------------------------------------------------
min(TSeg1, TSeg2)
[2 x (13 x bit_time - TSeg2)]
-----------------------------------------------------------------------
CAN Bit Timing
1051
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Controller Area Network (DCAN) Module
The resulting configuration is written into the Bit Timing Register:
Tseg2 = Phase_Seg2-1
Tseg1 = Pha Prop_Seg-1
SJW = SynchronizationJumpWidth-1
BRP = Prescaler-1
23.3.2.2 Example for Bit Timing at High Baudrate
In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s.
t
q
100
ns
=
t
CAN_CLK
delay of bus driver
60
ns
delay of receiver circuit
40
ns
delay of bus line (40m)
220
ns
t
Prop
700
ns
=
INT (2 × 1) = 7 × t
q
t
SJW
100
ns
=
1 × t
q
t
TSeg1
800
ns
=
t
Prop
+ t
SJW
t
TSeg2
100
ns
=
Information Processing Time + 1 × t
q
t
Sync-Seg
100
ns
=
1 × t
q
bit time
1000
ns
=
t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for CAN_CLK
1.58
%
=
(34)
=
(35)
=
0.38%
In this example, the concatenated bit time parameters are (1-1)
3
& (8-1)
4
& (1-1)
2
& (1-1)
6
, so the Bit
Timing Register is programmed to 0000 0700h.
23.3.2.3 Example for Bit Timing at Low Baudrate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
t
q
1
µs
=
2 × t
CAN_CLK
delay of bus driver
200
ns
delay of receiver circuit
80
ns
delay of bus line (40m)
220
ns
t
Prop
1
µs
=
1 × t
q
t
SJW
4
µs
=
4 × t
q
t
TSeg1
5
µs
=
t
Prop
+ t
SJW
t
TSeg2
3
µs
=
Information Processing Time + 3 × t
q
t
Sync-Seg
1
µs
=
1 × t
q
bit time
9
µs
=
t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for CAN_CLK
0.43
%
=
(36)
=
(37)
=
1.32%
In this example, the concatenated bit time parameters are (3-1)
3
& (5-1)
4
& (4-1)
2
& (2-1)
6
, so the Bit
Timing Register is programmed to 0000 24C1h.
