Power Domains
202
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Power Management Module (PMM)
PMM consists of several key components:
•
Register interface – the PMM control registers are mapped to the device memory space and start at
address 0xFFFF0000.
•
System Interface – the PMM receives the clocks, resets, errors and all other control signals through
this interface.
•
PSCON Diagnostic Compare – this block compares the outputs of each primary PSCON and the
respective diagnostic PSCON implemented for failsafe safety.
•
Self-Test Diagnostic – this block contains the logic to place the PSCON diagnostic compare block in a
self-test mode in order to test the failsafe feature.
•
Clock management – the PMM provides independent clock gating and handshaking controls for each
power domain and also generates the clock domains for each power domain.
•
Reset Management – the PMM provides independent reset signals for each power domain.
•
Power State Controller (PSCON) – The PSCON is a finite state machine that controls the power
sequence of a power domain from one state to another. Each power domain is controlled by one
dedicated PSCON.
•
Power Domain – A power domain is a group of logic and/or memories which is separated from the
global power supply via power switches. These power switches are controlled by the PSCON and can
be turned on or off.
3.2
Power Domains
shows the core and memory power domains implemented on the microcontroller.
This device has 8 separate core power domains:
•
PD1 is an always-ON domain and is not controlled by PMM. It contains the CPU as well as other
principal modules and the interconnect required for operation of the microcontroller. This domain also
includes 64KB of the tightly-coupled RAM. The PD1 can operate on its own even when all the other
core power domains are turned off by the PMM. Note that all I/Os are in this always-ON domain as
well.
Core power domains PD2 through PD5 and RAM_PD1 through RAM_PD3 are controlled by the PMM.
•
PD2 contains the Embedded Trace Macrocell (ETM-R4), RAM Trace Port (RTP), and Data
Modification Module (DMM) components of the debug sub-system as well as the Parameter Overlay
Module (POM).
•
PD3 contains some additional peripheral modules as an enhanced configuration over and above the
peripheral set available in PD1. These include a second High-End Timer (NHET2) with its dedicated
transfer unit (HTU2), a second Analog-to-Digital Converter (ADC2), a Serial Communication Interface
(SCI), an Inter-Integrated Circuit controller (I2C), a third Controller Area Network controller (DCAN3),
and a fourth Serial Peripheral Interface module (SPI4).
•
PD5 contains the Ethernet controller (EMAC), the External Memory Interface (EMIF), as well as some
components of the interconnect fabric required by these modules.
•
RAM_PD1, RAM_PD2 and RAM_PD3 each contain 64KB of tightly-coupled RAM.
NOTE:
Switching of Power Domains
The microcontrollers only support static switching of the power domains. That is, the power
domains can be turned ON or OFF one time during device initialization. Once configured, it is
not allowed to change the state of a power domain without first asserting a system reset.
