Transmit buf 0
Transmit buf 1
Transmit buf 127
Receive buf 0
Receive buf 1
Receive buf 127
E0
E1
E127
Control 0
Control 1
Control 127
Status 0
Status 1
Status 127
MIBSPI FIFO organization
0x0
0x4
0x400
31
1615
0
64-bit memory organization
E1
E0
E3
E2
0x0
0x8
63
0
E126
E127
E124
E125
E6
E7
E4
E5
In this example, a read of the MIBSPI FIFO is illustrated and assumes the following setup:
Read Element Size = 16 bit
Write Element Size = 64 bit
Element Count = 128
Frame Count = 1
Source Element Index = 4
Source Frame Index = 0
Destination Element Index = n/a, use post increment addressing mode
Destination Frame Index = n/a, use post increment addressing mode
Module Operation
552
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
Figure 16-13. Example of DMA Data Packing
For example, if the read element size is 8 bits, the element transfer count is equal to 9, and the write
element size is 64 bit. The DMA controller would first perform eight 8-bit read transactions from the
source. It would then perform a 64-bit write to the destination. When the same channel wins arbitration
again, the DMA controller would first perform one 8-bit read from the source, followed by one 8-bit write to
the destination, even though the write element size is 64 bit.
NOTE:
Since peripherals are slower, it is advised to use data packing feature with caution for
reading data from peripherals. Improper use might delay servicing other pending DMA
channels.
