Transmit buf 0
Transmit buf 1
Transmit buf 127
Receive buf 0
Receive buf 1
Receive buf 127
E0
E1
E127
Control 0
Control 1
Control 127
Status 0
Status 1
Status 127
MIBSPI FIFO organization
64-bit memory organization
0x0
0x4
0x400
E3
E2
E1
E0
0x0
0x8
63
0
31
1615
0
E124
E125
E126
E127
E4
E5
E6
E7
In this example, initialization of the MIBSPI FIFO is illustrated and assumes the following setup:
Read Element Size = 64 bit
Write Element Size = 16 bit
Element Count = 32
Frame Count = 1
Source Element Index = n/a, use post increment addressing mode
Source Frame Index = n/a, use post increment addressing mode
Destination Element Index = 4
Destination Frame Index = 0
Module Operation
551
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
Figure 16-12. Example of DMA Data Unpacking
When the read element size is smaller than the write element size, the DMA controller needs to perform
data packing. The number of elements to pack is equal to the ratio between the write element size and
read element size. In the example in
, the read element size is 16 bits and the write element
size is 64 bits. The DMA controller would first pack the first four elements by performing four consecutive
16-bit read accesses of E0, E1, E2, and E3 into the first word of the DMA's internal FIFO. The DMA
controller would then perform one single 64-bit write operation to transfer the data to the 64-bit destination
memory.
Normally, the DMA controller carries out bus transactions on the bus according to the element size. For
example, the DMA controller would perform a 16-bit read transaction if the read element size is
programmed as 16 bits, or an 8-bit write transaction if the write element size is programmed as 8 bit. The
exception is when the total transfer size is as defined in
is not a multiple of the write element
size.
