Frame Start
DCP Disable
Request
Busy Bit
Module Operation
973
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
21.2.1.4 General Control Packet Behavior
The action defined by the selected mode will be performed at the end of the last frame, which has the
frame counter value of 1. The one shot and auto switch mode will automatically update the CPENA
register at this time. Note, that for all three modes listed above, it is possible to switch to the other buffer
by writing to CPENA before the end of the current buffer is reached.
If a write access to CPENA happens while the last frame of DCP x (with frame counter = 1) is transferred
then the priority is defined by
(1)
See read table of CPENA register (
Table 21-1. CPENA / TMBx Priority Rules
Write access to CPENA bits (2 × x+1) and (2 × x) during the
frame with frame counter = 1
(1)
Priority Rule
Disable:
01 --> 00 or
10 --> 00
Disabling the DCP by the write to CPENA has priority, TMBx is
ignored.
Stay:
01 --> 01 or
10 --> 10
The write access to CPENA is ignored, TMBx has priority and
defines the action.
Switch:
01 --> 10 or
10 --> 01
Switching the DCP by the write to CPENA has priority, TMBx is
ignored.
There could be a case where the CPU wants to do main memory operations, but does not want the HTU
modifying the main memory. It could happen that a request was already active, but the frame transfer
hasn't started yet when the application disabled the control packets. The timing diagram in
shows this scenario.
Figure 21-8. Timing for Disabling Control Packets
Since the request for the transfer was already received before the DCPx is disabled, the HTU will still start
the frame transfer. The application would poll the BUSYx bit during the time the DCPx was disabled and
before the frame was started and would read a non-busy information. It then would start the main memory
operations thinking all transfers have completed, however after some time the HTU will start the
outstanding frame transfer and corrupt the main memory.
To avoid this, the application can set the VBUSHOLD bit to disable all transactions between the HTU and
the main memory. It has to poll the BUSBUSY bit to ensure that no outstanding transactions on the bus
are pending. The HTU will still receive all transfer requests from the N2HET, but it will not be able to
transfer any data to or from the main memory, while the VBUSHOLD bit is set.
21.2.2 Arbitration of HTU Elements and Frames
•
Frames do not interrupt each other. If a request occurs on DCP x while another frame runs on DCP y
(and x
≠
y), then the current frame completes before the new frame starts.
•
If two or more request lines are active, the request line with the lower number (specified in the request
number field of the corresponding N2HET instruction) is serviced first.
