SCI/LIN Control Registers
1279
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
25.13.3 SCI Global Control Register 2 (SCIGCR2)
The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate
a wakeup and for low-power mode control of the LIN module.
and
illustrate this
register.
Figure 25-29. SCI Global Control Register 2 (SCIGCR2) [offset = 08h]
31
18
17
16
Reserved
CC
SC
R-0
R/WL-0
R/WL-0
15
9
8
7
1
0
Reserved
GEN WU
Reserved
POWERDOWN
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; -
n
= value after reset
Table 25-14. SCI Global Control Register 2 (SCIGCR2) Field Descriptions
Bit
Field
Value
Description
31-18
Reserved
0
Reads return 0. Writes have no effect.
17
CC
Compare checksum. This bit is effective in LIN mode only. This bit is used by the receiver for
extended frames to trigger a checksum compare. The user will initiate this transaction by writing a
one to this bit. CC bit has to be set only after RX_RDY flag is set for the last received data.
In non-multi-buffer mode, when the CC bit is set, the checksum will be compared on the byte that is
expected to be the checksum byte.
During multi-buffer mode, the following scenarios are associated with the CC bit:
a) If the CC bit is set during the reception of the data, then the byte that is received after the
reception of the programmed number of data bytes as indicated by SCIFORMAT[18:16] is treated
as a checksum byte.
b) If the CC bit is set during the idle period (that is, during the inter-frame space), then the
immediate next byte will be treated as a checksum byte.
c) CC bit will be auto cleared after the checkbyte has been received and compared. Checksum
reception is not guaranteed if CC bit is write cleared by software during the checksum reception.
See
for more details.
0
No checksum compare will occur.
1
Compare checksum on expected checksum byte.
16
SC
Send checksum byte. This bit is effective in LIN mode only. This bit is used by the transmitter with
extended frames to send a checksum byte. In non-multi-buffer mode, the checksum byte will be
sent after the current byte transmission. In multi-buffer mode, the checksum byte will be sent after
the last byte count, indicated by the SCIFORMAT[18:16]). See
for more details. This
byte will be cleared after the checksum byte has been transmitted.
In non-multi-buffer mode, the checksum byte will be sent after the current byte transmission.
During multi-buffer mode, the following scenarios are associated with the SC bit:
a) The checkbyte will be sent after the last byte count, indicated by the SCIFORMAT[18:16]).
b) Checksum will not be sent if SC is set before transmitting the very first byte(that is, during
interframe space).
c) SC bit will be auto cleared after the checkbyte has been transmitted. Checksum transmission is
not guaranteed if SC bit is write cleared by software during the checksum transmission. See
for more details.
0
No checksum byte will be sent.
1
A checksum byte will be sent.
15-9
Reserved
0
Reads return 0. Writes have no effect.
8
GEN WU
Generate wakeup signal. This bit is effective in LIN mode only. This bit controls the generation of a
wakeup signal, by transmitting the TDO buffer value. The LIN protocol specifies that this signal
should be a dominant for T
WUSIG
. This bit is cleared on reception of a valid synch break.
0
No wakeup signal will be generated.
1
The TDO buffer value will be transmitted for a wakeup signal. The bit will be cleared on a SWnRST.
7-1
Reserved
0
Reads return 0. Writes have no effect.
