Control Registers
272
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
F021 Flash Module Controller (FMC)
Table 5-19. Flash Error Detection and Correction Status Register (FEDACSTATUS)
Field Descriptions (continued)
Bit
Field
Value
Description
17
B2_UNC_ERR
Bus 2 Uncorrectable Error Flag
0
No bus 2 uncorrectable errors were detected.
1
A bus 2 uncorrectable error was detected.
Two or more bits in the data, or ECC field; or a single-bit error in the address field have
been found in error. Address-bit errors are considered an uncorrectable error. The
FUNC_ERR_ADD register should contain the Bus 2 error location. This error will generate
an ESM group 3 channel 7 event.
16
B2_COR_ERR
Bus 2 Correctable Error Flag
0
No bus 2 correctable error was detected.
1
A bus 2 correctable error was detected.
One bit in the data, or ECC field has been found in error. Either the ERR_ONE_FLAG or
ERR_ZERO_FLAG should be set in this register along with this bit. The FCOR_ERR_ADD
register should contain the error address, and the FCOR_ERR_POS register should contain
the failing bit position. This error will generate an ESM group 1 channel 6 event.
15-13
Reserved
0
Reads return 0. Writes have no effect.
12
D_UNC_ERR
Diagnostic Uncorrectable Error Flag
This bit sets when diagnostic mode 1 discovers a multi-bit error using the ECC. This means
two or more bits in the data, address or ECC field have been found in error. The ECC is
capable of correcting a single-bit error and this would show up in the D_COR_ERR bit. The
ECC can always detect two bit errors. Three or more bit errors may escape detection with
the ECC. This bit also may set during other uncorrectable errors and during the diagnostic
mode like address tag errors and ECC malfunctions.
11
ADD_TAG_ERR
Address Tag Register Error Flag
0
No address tag register error was detected.
1
An address tag register error was detected.
This bit is set if the primary address tag has a hit but the duplicate address tag does not
match the primary address tag. This bit is functional only when pipeline mode is enabled.
This error will create an ESM group 3 channel 7 event.
10
ADD_PAR_ERR
Address Parity Error Flag
0
No address parity error was detected.
1
A parity error was detected on the incoming address bus.
The full 32 bit address will be stored in FUNC_ERR_ADD register. This error will create an
ESM group 2 channel 4 event.
9
Reserved
0
Reads return 0. Writes have no effect.
8
B1_UNC_ERR
Bus 1 Uncorrectable Error Flag
0
No bus 1 uncorrectable errors were detected.
1
A bus 1 uncorrectable error was detected.
Two or more bits in the data, or ECC field; or a single-bit error in the address field have
been found in error. Address-bit errors are considered an uncorrectable error. The
FUNC_ERR_ADD register will contain the Bus 1 error location. This error will generate an
ESM group 3 channel 7 event..
7-4
Reserved
0
Reads return 0. Writes have no effect.
3
D_COR_ERR
Diagnostic Correctable Error Status Flag
This bit sets when diagnostic mode 1 discovers a single-bit correctable error using the ECC.
Multi-bit errors are flagged using the D_UNC_ERR bit. The uncorrectable error address
must be unfrozen in order to set this bit.
