Control Registers and Control Packets
600
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
16.3.1.52 Parity Control Register (DMAPCR)
Figure 16-68. Parity Control Register (DMAPCR) [offset = 1A8h]
31
15
16
Reserved
ERRA
R-0
R/WP-0
15
9
8
7
4
3
0
Reserved
TEST
Reserved
PARITY_ENA
R-0
R/WP-0
R-0
R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -
n
= value after reset
Table 16-60. Parity Control Register (DMAPCR) Field Descriptions
Bit
Field
Value
Description
31-17
Reserved
0
Reads return 0. Writes have no effect.
16
ERRA
Error action.
0
If a parity error is detected on control packet x (x = 0, 1, ... n), then the enable/disable state of
control packet x remains unchanged.
1
If a parity error is detected on control packet x (x = 0, 1, ...n), then the DMA controller is
disabled immediately. If a frame on control packet x is processed at the time the parity error is
detected, then remaining elements of this frame will not be transferred anymore. The DMA will
be disabled regardless of whether the error was detected during a read to the control packet
RAM performed by the DMA state machine or by a different master.
15-9
Reserved
0
Reads return 0. Writes have no effect.
8
TEST
When this bit is set, the parity bits are memory mapped to make them accessible by the CPU.
0
The parity bits are not memory mapped.
1
The parity bits are memory mapped.
7-4
Reserved
0
Reads return 0. Writes have no effect.
3-0
PARITY_ENA
Parity error detection enable. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and a
parity error is detected, the DMA_UERR signal is activated.
5h
The parity check is disabled.
All other
values
The parity check is enabled.
Note: It is recommended to write Ah to enable parity check, to guard against soft error
from flipping PARITY_ENA to a disable state.
