DEST[1]
SIZE[1]
ADDR[15] ADDR[11]
ADDR[7]
ADDR[3]
DATA[7]
DATA[3]
DEST[0]
ADDR[13]
ADDR[6]
ADDR[2]
DATA[2]
DATA[6]
DATA[5]
DATA[4]
ADDR[9]
ADDR[5]
ADDR[1]
DATA[1]
ADDR[4]
ADDR[0]
DATA[0]
SIZE[0]
ADDR[14] ADDR[10]
ADDR[12]
ADDR[8]
STAT[1]
STAT[0]
ADDR[17]
ADDR[16]
RTPCLK
RTPSYNC
RTPDATA[0]
RTPDATA[1]
RTPDATA[2]
RTPDATA[3]
RTPSYNC
RTPDATA
RTPCLK
RTPENA
Packet1
Packet2
Packet3
Packet4
Packet1
Packet2
Module Operation
1712
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
31.2.5 Signal Description
RTPCLK
This clock signal is used to clock out the data of the serializer. Depending on the CONTCLK bit,
the clock can be suspended between packets or it can be free running. The RTPCLK frequency
can be adjusted by the PRESCALER bits (see
).
RTPSYNC
The module provides a packet-sync signal. This signal will go high on the rising edge of RTPCLK
and will be valid for one RTPCLK cycle to synchronize external hardware to the data stream. The
RTPSYNC pulse will be generated for each new packet.
RTPENA
This signal is an input and can be used by external hardware to stop the data transmission
between packets. When the RTPENA signal goes high, the RTP will finish the current packet
transmission and then stop. Once the signal is pulled low again, the RTP will resume the transfer
if data is still present in the serializer or FIFOs. The RTPENA signal does not have to be used for
proper module operation. It can be used in GIO mode if the external hardware cannot generate
this signal. Overflows of the external system cannot be handled in this case.
RTPDATA[15:0]
These pins are used to do the actual data transfer. Data changes with the rising edge of RTPCLK.
The port can be configured for different widths (PW[1:0]). The minimum port width supported is 2
pins. See
which pins are used for the port.
shows an example of multiple packet transmissions in Trace Mode with an interruption
between packets because of RTPENA pulled high.
Figure 31-7. RTP Packet Transfer with Sync Signal
shows an example of a 4-bit data port with 8-bit write data (A5h) written into RAM1 (address
12345h) with no overflow in trace mode.
Figure 31-8. Packet Format in Trace Mode
