Interrupt Vector Table (VIM RAM)
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SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Vectored Interrupt Manager (VIM) Module
There is one bit of parity per 32-bit ISR address. When a write is performed into the interrupt vector table,
the parity is calculated for the 32-bit word and a parity bit is written into the corresponding parity region of
interrupt vector table.
NOTE:
Only 32-bit write/read access are allowed on interrupt vector table if parity is required. Non
32-bit access might result in parity errors.
When a read occurs from the CPU or VIM, the VIM calculates the parity from the data coming from the
interrupt vector table and compares it to the parity stored in the table. The access of the data and the
parity is performed in the same clock cycle.
If the parity bit does not match the calculated parity, a parity error is generated and the VIM stores the
address of the error in the ADDERR register. The parity flag error (PARFLG) is set.
NOTE:
The PARFLG register is only for bypassing the interrupt vector table in case of a parity fault.
It should be used only to maintain the interrupt vector table bypassed. The checking of the
parity fault should be done in the error signaling module (ESM) module where all parity
errors are flagged.
Since the interrupt vector table may have an error, the FBPARERR register will provide to the VIC port,
IRQVECREG and FIQVECREG, a fall-back address to an ISR that can restore the interrupt vector table
content. The FBPARERR register should be set before initializing the interrupt in the interrupt vector table,
to avoid branching to an unpredictable location.
The normal operation is restored when the PARFLG is cleared by the CPU. It is recommended to restore
the content of the VIM before clearing the PARFLG.
The parity error signal is forwarded to the ESM.
15.4.2 Enabling and Controlling the VIM Parity
The polarity of VIM parity is controlled by the DEVCR1 register in the system module (address
FFFF FFDCh). The parity enable is controlled by the PARCTL register. After reset, the parity is disabled.
Parity checking can be enabled by writing 0xA (1010b) in the PARENA[3:0] bit field of the PARCTL
register. The default polarity is odd. The polarity can be changed to even by writing 5 (0101b) in the
DEVPARSEL[3:0] bit field of the DEVCR1 register.
15.4.3 Interrupt Vector Table Initialization
After reset, the interrupt vector table content including the parity bits is not initialized. Therefore, the CPU
needs to initialize all of the interrupt addresses into the table, before enabling the corresponding interrupt
channel. If parity is required, this initialization should be done after the parity functionality is enabled. In
this way, the corresponding parity bit will be automatically updated. This initialization is only required when
vectored interrupts are used, index interrupt management does not need the table to be initialized.
