USB Device Controller
1607
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
29.3.7.2 Autodecoded Control Read Transfers
Autodecoded control reads include the standard device requests GET_ENDPOINT and
DEVICE_STATUS. These control read transfers access information that is kept in registers inside the USB
module, so CPU code is not involved in filling the read data into the TX FIFO.
The USB module returns the currently selected appropriate status information (depending on the wIndex
value in the setup stage data packet) during the data phase of the single IN transaction of the data stage,
and provides ACK as the handshake for the status stage handshake phase. The CPU receives no
interrupt.
29.3.7.2.1 Autodecoded Control Read Transfer Handshaking
The USB device controller module automatically provides ACK handshaking for all transactions of all
stages of autodecoded control read transfers, except if a corrupted token packet is received, which the
USB module ignores. The CTRL.FIFO_EN and SYSCON2.STALL_CMD bits have no effect on the
handshaking. If the status packet has a DATA0 PID instead of a DATA1 PID, status is STALLed and no
interrupt is asserted to the CPU. If the setup packet has a DATA1 PID instead of a DATA0 PID, setup
transaction is ignored (error).
29.3.7.2.2 Autodecoded Control Read Transfer Error Conditions
If the token phase or the data phase of a setup stage transaction has an error (bad CRC, PID check, or bit
stuffing error), the USB block ignores the transaction. The USB block does not provide ACK handshaking
in this case.
Data errors during the data stage of autodecoded control write transfers are handled in the standard way;
any data stage transaction from the host where a data error occurs is ignored.
It is possible that the USB host sends a GET_ENDPOINT/DEVICE_STATUS request with a bad
parameter. If the autodecode mechanism senses a bad parameter in the setup stage data phase, the
autodecode mechanism causes a STALL handshake to be signaled during the data phase of the data
stage and during the status stage.
29.3.7.3 Non-Autodecoded Control Write Transfers
Non-autodecoded control write transfers include the SET_/CLEAR_ENDPOINT feature,
SET_CONFIGURATION, SET_INTERFACE, SET_DESCRIPTOR and class- or vendor-specific control
write transfers. Non-autodecoded control write transfers consist of two or three stages [setup, data
(optional), and status].
The setup stage of a valid non-autodecoded control write transfer consists of one SETUP transaction from
USB host to USB device. At the end of the setup stage handshake, the USB module generates an CPU
general USB interrupt with the IRQ_SRC.SETUP flag set. The CPU must respond to this general USB
interrupt by setting EP_NUM.SETUP_SEL bit, which clears the setup interrupt flag. The CPU must then
read 8 bytes from the setup FIFO via the DATA register, clear EP_NUM.EP_SEL bit, and check the
IRQ_SRC.SETUP flag. If the IRQ_SRC.SETUP flag is set, the CPU must discard the setup data it has just
read and handle the new setup data packet following the same scheme. If the IRQ_SRC.SETUP flag is
cleared, the CPU code interprets this request information and performs any application-specific activity
needed because of the setup stage request. If there is one or more data stage for the transfer, the CPU
must set the CTRL.SET_FIFO_EN bit for endpoint 0 to allow the core to accept RX data from the coming
OUT transaction.
The data stage for non-autodecoded control writes consists of zero or more OUT transactions.
Transaction handshaking and interrupt generation as for non-isochronous, non-control OUT endpoints
applies. The CPU can cause NAK, STALL, or ACK signaling for the data stage transactions. If ACK was
signaled on a given general USB interrupt, the CPU must respond by reading the data from the endpoint 0
RX FIFO and saving it for processing.
