Control Registers
1190
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.9.27 TG Interrupt Enable Set Register (TGITENST)
The register TGITENST contains the TG interrupt enable flags for transfer-finished and for transfer-
suspended events. Each of the enable bits in the higher half-word and the lower half-word of TGITENST
belongs to one TG.
The register map shown in
and
represents a super-set device with the
maximum number of TGs (16) assumed. The actual number of bits available varies per device.
Figure 24-56. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]
31
16
SETINTENRDY[15:0]
R/W-0
15
0
SETINTENSUS[15:0]
R/W-0
LEGEND: R/W = Read/Write; -
n
= value after reset
Table 24-35. TG Interrupt Enable Set Register (TGITENST) Field Descriptions
Bit
Field
Value
Description
31-16
SETINTENRDY[
n
]
TG interrupt set (enable) when transfer finished. Bit 16 corresponds to TG0, bit 17 corresponds
to TG1, and so on.
0
Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when
TGx completes.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx
completes.
Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx completes.
15-0
SETINTENSUS[
n
]
TG interrupt set (enabled) when transfer suspended. Bit 0 corresponds to TG0, bit 1
corresponds to TG1, and so on.
0
Read: The TGx-completed interrupt is disabled. This interrupt does not get generated when
TGx is suspended.
Write: A write of 0 to this bit has no effect.
1
Read: The TGx-completed interrupt is enabled. The interrupt gets generated when TGx is
suspended.
Write: Enable the TGx-completed interrupt. The interrupt gets generated when TGx is
suspended.