Module Operation
969
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
21.2.1 Data Transfers between Main RAM and N2HET RAM
21.2.1.1 Addressing Modes
The addressing modes of a control packet need to be distinguished between the main RAM of the CPU
and the N2HET RAM.
Main RAM
For each double control packet (see
), the addressing mode for the main RAM (RAM0/1)
can be configured to constant or post-increment mode in register IHADDRCT.
•
Constant Addressing:
In constant mode, the HTU writes/reads the data to/from the same address in
the main RAM.
•
Post-increment Addressing:
In post-increment mode, the HTU writes/reads the data to/from the main
RAM by incrementing through the addresses after each transfer. If 32-bit transfers are selected it will
automatically increment by 4 Byte, if 64-bit transfers are selected, it will increment by 8 Byte. The
examples of Use Cases illustrate the post-increment mode, where the elements of consecutive frames
are transferred to/from consecutive locations in the main RAM buffer.
N2HET RAM
How a DCP addresses the N2HET RAM is determined by the initial N2HET address, the initial element
counter (IETCOUNT) and the N2HET addressing mode (ADDMH). The main difference to the main RAM
addressing mode is that the HET address is reset to the initial HET address for every first element of a
frame. To implement constant addressing, the initial element counter needs to be set to 1. Post-increment
addressing is selected by programming the initial element counter to a value other than 1.
21.2.1.2 Single Buffer Implementation
In a single buffer implementation, the DCP is set up to transfer data to/from a single buffer in the main
RAM. With each transfer request, the programmed number of elements is transferred and the buffer
pointer is reset to its starting address after the programmed number of frame transfers have completed.
shows the request on one request line of the HTU and the frame running on the assigned
control packet visualized by the element counter. In the diagram, the frame has 5 element transfers
(element count = 5).
Before the application reads the buffer, it has to disable the control packet to avoid that new data
overwrites the buffer while it's being accessed by the application. Regardless of the control packet being
disabled at t1 or t2 the last frame will always be completed, since the trigger request has been received
already. The application can determine any ongoing transfers by the TIPF flag and the NACP bits.
•
One Shot Buffer Mode:
If TMBA or TMBB is set to one shot buffer mode then the data stream will
stop after all elements of buffer A or buffer B have been transferred. This means that the
corresponding DCP will be disabled after the last frame was transferred to/from buffer A or B and
CFTCTA or CFTCTB decrements to 0.
•
Circular Buffer Mode:
If TMBA or TMBB is set to circular buffer mode, then the data stream will
continue back at the start of buffer A or B after all elements of buffer A or B have been transferred. The
example of Timing Example for Circular Buffer Mode assumes IETCOUNT = 3 (Initial Element Transfer
Count), IFTCOUNT = 3 (Initial Frame Transfer Count, SIZE = 0 (Size of Transfer = 32-bit) and
ADDFM = 0 (Addressing Mode Main Memory = Post Increment). So there are in total 9 32-bit values in
the buffer. It also assumes IFADDRx = 10h. "U" means uninitialized.
