Memory Test Algorithms on the On-chip ROM
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SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Programmable Built-In Self-Test (PBIST) Module
4.
DOWN1a:
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The Down1 pattern forces the switching of all data bits and most address bits on consecutive read
cycles. This is primarily a read/write test of the CPU/memory subsystem.
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The aggressive writes target at-speed write failures.
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It also targets row/column decode in the memory array.
•
Targets the sense amps and sense amp multiplexors.
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Memory array output buffers.
•
This algorithm operates as follows:
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Load 1st half of the memory under test with one pattern.
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Load 2nd half of the memory under test with the bit-wise inverse of the pattern.
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Alternate sequential reads sequences between one sequence starting at the beginning of the
array and a second sequence starting at the end of the array.
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Upon completion of the read back, invert the patterns in both halves of the array and repeat the
above step.
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Perform an aggressive write sequence by alternating writes between the bottom half of the
memory upwards with a data pattern and the top half of the memory downwards with the
inverse data pattern.
–
Invert the data pattern for the above two steps to perform another sequence of aggressive
writes.
5.
DTXN2a:
This algorithm is used to target the global column decode Logic.
