USB Device Controller
1603
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
29.3.6.1 Isochronous IN Endpoint Handshaking
Because isochronous endpoint transactions have no handshake packets, the STAT_FLG.STALL,
STAT_FLG.NAK, and STAT_FLG.ACK bits for isochronous endpoints always return 0. Because there is
no handshake, there is no endpoint-specific interrupt to the CPU to report handshake results for
isochronous endpoints.
29.3.6.2 Isochronous IN Transaction Error Conditions
If the USB host did not successfully complete an ISO IN transaction in the previous frame, and if data
were present in TX FIFO to be sent at the IN transaction, the STAT_FLG.MISS_IN bit is asserted for the
duration of the following frame. If the ISO IN endpoint is cleared in the middle of a USB transaction to the
background FIFO, the macro forces a bit stuffing error for the ISO transaction.
29.3.6.3 Isochronous IN Endpoint FIFO Error Conditions
If the CPU attempts to overfill the configured endpoint FIFO, data written to DATA register after the TX
FIFO is full is lost, but any data that was successfully put into the FIFO is transmitted when that FIFO is
the background FIFO and an IN transaction for that endpoint occurs. Because an ISO TX FIFO is cleared
automatically on the toggle from background to foreground, there is no reason to clear the FIFO. However,
if the CPU does not wish to send the data it wrote, clearing the endpoint is the only mechanism to do this.
29.3.7 Control Transfers on Endpoint 0
Control transfers on endpoint 0 include control write and control read transfers. Control write and control
read transfers are each composed of two or more transactions to endpoint 0. Additionally, the USB device
controller module is capable of autodecoding some control write and control read transfers. These
operations are summarized in
and
. An IN or an OUT transaction is received out
of a control request. This transaction is automatically stalled by the core.
Non-autodecoded control read and control write transfers are sets of transactions that occur on endpoint 0
and have specific USB protocol meaning but are not handled automatically by the core. The USB device
controller block automatically provides an ACK handshake for the setup stage transaction, but the data
and status stage transaction handshaking is accomplished using the usual RX and TX control bits that
affect transaction handshaking. A general USB interrupt to the CPU occurs at the end of each transaction
of each stage of a control transfer. The CPU must perform the following actions to act on non-
autodecoded control transfers:
•
Process the setup phase setup USB interrupt. The CPU reads the control transfer command from the
setup FIFO and decodes the command. For control reads, the CPU fetches the requested read data
and places it (or as much of the read data as fits) into the endpoint 0 FIFO, and then enables the
endpoint 0 FIFO. For control writes, the CPU code only enables the endpoint 0 FIFO. CPU code also
sets any flags needed for processing endpoint 0 USB interrupts during the control transfer.
•
Process the data phase endpoint 0 general USB interrupt(s). For control reads, the data phase general
USB endpoint 0 TX interrupt indicates that the previously provided transmit data has been sent. Any
additional data must be written to the endpoint 0 FIFO. For control writes, the write data must be pulled
from the endpoint 0 FIFO, and when all control write data is available, interpret the write data and act
on the write request. After handling the last data phase interrupt, the CPU must set the endpoint 0
control bits to signal the desired status to the host.
•
Process the status stage endpoint 0 general USB interrupt. The CPU provides its completion status
back to the USB host during this stage, either via status in the data phase of the transaction (for
control write transfers) or via the handshake phase of the transaction (for control read transfers).
