Operating Modes
1130
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
24.2.9 Decoded and Encoded Chip Select (Master Only)
In this device, the SPI can connect to up to 6 individual slave devices using chip-selects by routing one
wire to each slave. The 6 chip selects in the control field are directly connected to the 6 pins. The default
value of each chip select (not active) can be configured via the register CSDEF. During a transmission,
the value of the chip select control field (CSNR) of the SPIDAT1 register (SPIDAT1) is driven on the
SPICS pins. When the transmission finishes, the default chip-select value (defined by the CSDEF register)
is put on the SPICS pins.
The SPI can support more than 6 slaves by using encoded chip selects. To connect the SPI with encoded
slaves devices, the CSNR field allows multiple active SPICS pins at the same time, which enables
encoded chip selects from 0 to 16. To use encoded chip selects, all 6 chip select lines have to be
connected to each slave device and each slave needs to have a unique chip-select address. The CSDEF
register is used to provide the address at which slaves devices are all de-selected.
Users can combine decoded and encoded chip selects. For example,
n
SPICS pins can be used for
encoding an
n
-bit address and the remaining pins can be connected to decoded-mode slaves.
24.2.10 Variable Chip Select Setup and Hold Timing (Master Only)
In order to support slow slave devices, a delay counter can be configured to delay data transmission after
the chip select is activated. A second delay counter can be configured to delay the chip select deactivation
after the last data bit is transferred. Both delay counters are clocked with the peripheral clock (VCLK).
If a particular data format specifically does not require these additional set-up or hold times for the chip
select pins, then they can be disabled in the corresponding SPIFMTx register.
24.2.11 Hold Chip-Select Active
Some slave devices require the chip select signal to be held continuously active during several
consecutive data word transfers. Other slave devices require the chip select signal to be deactivated
between consecutive data word transfers.
CSHOLD is programmable in both master and slave modes of the multi-buffer mode of SPI. However, the
meaning of CSHOLD in master mode and slave mode are different.
NOTE:
If the CSHOLD bit is set within the current data control field, the programmed hold time and
the following programmed set-up time will not be applied between transactions.
24.2.11.1 CSHOLD Bit in Master Mode
Each word in a master-mode SPI can be individually initialized for one of the two modes via the CSHOLD
bit in its control field.
If the CSHOLD bit is set in the control field of a word, the chip select signal will not be deactivated until the
next control field is loaded with new chip select information. Since the chip-select is maintained active
between two transfers, the chip-select hold delay (T2CDELAY) is not applied at the end of the current
transaction, and the chip-select set-up time delay (C2TDELAY) is not applied as well at the beginning of
the following transaction. However, the wait delay (WDELAY) will be still applied between the two
transactions, if the WDEL bit is set within the control field.
shows the SPI pins when a master-mode SPI transfers a word that has its CSHOLD bit set.
The chip-select pins will not be deasserted after the completion of this word. If the next word to transmit
has the same chip-select number (CSNR) value, the chip select pins will be maintained until the
completion of the second word, regardless of whether the CSHOLD bit is set or not.
