CTRL
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overflow
Module Operation
1711
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
31.2.3.3 Cortex-R4 Specifics
Due to the bus system used on Cortex-R4, special considerations have to be taken into account.
shows the block diagram of the RTP connected to the Cortex-R4 RAM interface.
Both interfaces to RAM0 and RAM1 are 64-bit wide. RAM0 and RAM1 are building a consecutive address
range, where the 64-bit addresses 00, 10h, 20h, ... reside in RAM0 and 08h, 18h, 28h, ... reside in RAM1.
Considerations/Restrictions
•
To trace a certain address range, the regions of both RAM0 (
) and RAM1
) need to be set up for the same start address and region size. Otherwise only every
other 64-bit access will be traced.
•
Direct Data Mode read operation is not supported on Cortex-R4. This is because the CPU uses 64-bit
accesses for read operations even though the intended accesses is sub-64-bit wide. Since Direct Data
Mode only supports 32-bit data transfers and the Cortex-R4 RAM interface does not provide
information about which byte out of the 64-bit is accessed with the read operation, the RTP cannot
determine the correct data value.
•
If the RAM is protected by ECC, only 64-bit write accesses can be traced. Every 64-bit word in the
RAM is protected by a corresponding 8-bit ECC checksum. When a sub-64-bit write access is
performed, the Cortex-R4 has to do a read-modify-write operation of the 64-bit word to be modified in
order to calculate the corresponding checksum and then write it back to memory. External hardware
can still determine which portion of the 64-bit word has been modified, since the other bytes in this
word did not change.
31.2.4 Overflow/Empty Handling
In case the application does RAM accesses faster than the FIFO can be emptied via the external pin
interface, the FIFO can overflow. The user can choose whether the program execution/data transfer
should be suspended, or an overflow should be signaled in the status bits of the next, to be transmitted,
message of this particular FIFO. If program execution is resumed, the data will be lost. The overflow will
not be signaled in the message that is already in the serializer and being transmitted when the overflow
occurs.
NOTE:
The status information will only be transmitted in Trace Mode, since the Direct Data Mode
packet does not contain any status information.
When an overflow in a FIFO occurs, the corresponding bit in
will be set.
Figure 31-6. FIFO Overflow Handling
