frame counter
CFTCTx
element counter
request
2
1
buffer location
U
full address
CFADDRx
1Ch
28h
0
2
1
34h
1Ch
28h
U
busy bit
buffer full flag
BFINTFL
frame counter
CFTCTx
element counter
request
1
buffer location
full address
CFADDRx
busy bit
buffer full flag
BFINTFL
3
2
1
10h 14h 18h
3
2
1
1Ch 20h 24h
3
2
1
28h 2Ch 30h
3
2
1
10h 14h 18h
3
2
1
1Ch 20h 24h
3
2
1
28h 2Ch 30h
end of
buffer
end of
buffer
1 Buffer
X
5 4 3 2 1
1 2 3 4 5
X
X
15
14
13
12
11
10
9
8
15
15
15
15
15
15
7
6
5
4
3
2
1
TU request (1)
Element Counter
Element Number
t1
t2
Increasing
Address
Memory View
5 4 3 2 1
6 7 8 9 10
5 4 3 2 1
11 12 13 14 15
Module Operation
970
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
Figure 21-4. Single Buffer Timing and Memory Representation
Figure 21-5. Timing Example for Circular Buffer Mode