Module Operation
361
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
CPU Compare Module for Cortex-R4F (CCM-R4F)
9.3.2.1
Compare Match Test
During the Compare Match Test, there are four different test patterns generated to stimulate the CCM-
R4F. An identical vector is applied to both input ports at the same time expecting a compare match. These
patterns cause the self-test logic to exercise every CPU compare bus output signal in parallel. If the
compare unit produces a compare mismatch then the self-test error flag is set, the self-test error signal is
generated, and the Compare Match Test is terminated.
The four test patterns used for the Compare Match Test are:
•
All 1s on both CPU signal ports
•
All 0s on both CPU signal ports
•
0xAs on both CPU signal ports
•
0x5s on both CPU signal ports
These four test patterns will take four clock cycles to complete. illustrates the sequence of Compare Match
Test.
Table 9-1. Compare Match Test Sequence
CPU 1 Signal Position
CPU 2 Signal Position
Cycle
n:8
7
6
5
4
3
2
1
0
n:8
7
6
5
4
3
2
1
0
1s
1
1
1
1
1
1
1
1
1s
1
1
1
1
1
1
1
1
0
0s
0
0
0
0
0
0
0
0
0s
0
0
0
0
0
0
0
0
1
0xA
1
0
1
0
1
0
1
0
0xA
1
0
1
0
1
0
1
0
2
0x5
0
1
0
1
0
1
0
1
0x5
0
1
0
1
0
1
0
1
3
9.3.2.2
Compare Mismatch Test
During the Compare Mismatch Test, the number of test patterns is equal to twice the number of CPU
output signals to compare in lock step mode. An all 1s vector is applied to the CCM-R4F’s CPU1 input
port and the same pattern is also applied to the CCM-R4F’s CPU2 input port but with one bit flipped
starting from signal position 0. The un-equal vector will cause the CCM-R4F to expect a compare
mismatch at signal position 0, if the CCM-R4F logic is working correctly. If, however, the CCM-R4F logic
reports a compare match, the self-test error flag is set, the self-test error signal is asserted, and the
Compare Mismatch Test is terminated.
This Compare Mismatch Test algorithm repeats in a domino fashion with the next signal position flipped
while forcing all other signals to logic level 1. This sequence is repeated until every single signal position
is verified on both CPU signal ports.
The Compare Mismatch Test is terminated if the CCM-R4F reports a compare match versus the expected
compare mismatch. This test ensures that the compare unit is able to detect a mismatch on every CPU
signal being compared.
illustrates the sequence of Compare Mismatch Test. There is no error
signal is sent to ESM if the expected errors are seen with each pattern.
