Example Configuration
667
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
17.4.2.1.5 SDRAM Configuration Register (SDCR) Settings for the EMIF to K4S641632H-TC(L)70
Interface
Finally, the fields of the SDRAM configuration register (SDCR) should be programmed as described in
to properly interface with the K4S641632H-TC(L)70 device. Based on these settings, a value
of 4720h should be written to SDCR.
shows how SDCR should be programmed. The EMIF is
now ready to perform read and write accesses to the SDRAM.
Table 17-41. SDCR Field Values For the EMIF to K4S641632H-TC(L)70 Interface
Field
Value
Purpose
SR
0
To avoid placing the EMIF into the self refresh state
NM
1
To configure the EMIF for a 16-bit data bus
CL
011b
To select a CAS latency of 3
BIT11_9LOCK
1
To allow the CL field to be written
IBANK
010b
To select 4 internal SDRAM banks
PAGESIZE
0
To select a page size of 256 words
Figure 17-31. SDRAM Configuration Register (SDCR)
31
30
29
28
24
0
0
0
0 0000
SR
Reserved
Reserved
Reserved
23
18
17
16
00 0000
0
0
Reserved
Reserved
Reserved
15
14
13
12
11
9
8
0
1
0
0
011
1
Reserved
NM
Reserved
Reserved
CL
BIT11_9LOCK
7
6
4
3
2
0
0
010
0
000
Reserved
IBANK
Reserved
PAGESIZE
