]
[
4
5
]
[
20
]
[
5
4
]
[
20
MHz
MHz
NR
f
or
MHz
MHz
NR
f
CLKIN
CLKIN
=
=
=
=
40
2
³
´
=
´
s
CLKIN
f
NR
f
NS
NS
NR
f
f
CLKIN
s
´
´
º
2
40
³
´
s
CLKIN
f
NR
f
Modulation Period (1/f
s
)
M
o
d
u
la
ti
o
n
f
f
0
0
-n%
f
0
+n%
Time (Ps)
F
re
q
u
e
n
c
y
(M
H
z
)
D
e
p
th
Phase-Locked Loop Theory of Operation
390
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
10.7.4 Frequency Modulation
The output clock of the PLL changes frequency in a controlled way, centered around the unmodulated
output frequency. The modulation block directly modulates the VCO frequency at the loop filter, and
creates the triangular frequency modulation (see
).
Figure 10-12. Frequency vs. Time
10.8 Programming Example
This section provides an example of how to program the PLL. For non-modulation settings, the PLLCTL1
and PLLCTL2 settings from 130nm process devices can be used without modification.
Suppose that, using a 20MHz crystal, the application requires:
•
180MHz GCLK (and HCLK) frequency
•
100 kHz spreading frequency
•
0.5% spreading depth
1. Choose an NR and NS such that:
•
(14)
•
(15)
•
(16)
•
(NR,NS) = {(5,20), (4,25), (2,50), (1,100)}
•
Either NR = 5 and NS = 20 or NR = 4 and NS = 25 are reasonable. Another choice (NR = 3 and
NS = 33) is possible, if the modulation frequency can vary from 100KHz.
2. Choose Output CLK frequency as integer divider of output frequency near to 330MHz. Output CLK
frequency shall not exceed 550MHz or fall below 150MHz.
The integer values for 180MHz are 360MHz or 540MHz. 360MHz is close to the target frequency of
330MHz and we use this frequency.
3. In this case, either of the following equations are suitable choices for getting to 360MHz.
Choose NR = 5, NS = 20 and set NF = 90 or choose NR = 4, NS = 25 and set NF = 72.
(17)
