N2HET HR 0
HET[0]
0
0
1
HETAND0
HETAND0
N2HET HR 1
HET[1]
HET[0]
HR0
HR1
Asymmetrical
counter
(CNT)
Symmetrical
counter
(not in HET)
N2HET Functional Description
810
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
graphically shows the implementation of the XOR-shared feature. The first 2 waveforms
(symmetrical counter and CNT) show a symmetric counter and asymmetric counter. The symmetric
counter is shown only to highlight the axis of symmetry and is not implemented in the N2HET. The
asymmetric counter, which is implemented with a CNT instruction, needs to be set to the period of the
symmetric counter. The next two waveforms (HR [0] and HR [1]) show the output of the HR structures,
which are the inputs for the XOR gate to create the PWM output on pin HET[0]. Notice that the pulses of
signal HET[0] are centered about the axis of symmetry.
Figure 20-14. Symmetrical PWM with XOR-sharing Output
As an alternative, HR structures may be shared using a logical AND function to combine the effects of the
pin structures. The HETAND allows sharing two consecutive HR structures N (even) and N+1 (odd). See
. In this structure, pin N+1 remains available for general-purpose input/output.
NOTE:
Setting both the HETAND bit and HETXOR bits at the same time for a given pair of N2HET
pins is not supported, must be avoided by the application program.
Figure 20-15. AND-shared HR I/O
