Control Registers
293
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
F021 Flash Module Controller (FMC)
5.7.30 Parity Override Register (FPAR_OVR)
Figure 5-37. Parity Override Register (FPAR_OVR) [offset = 7Ch]
31
17
16
Reserved
BNK_INV_
PAR
R-0
R/WP-0
15
12
11
9
8
7
0
BUS_PAR_DIS
PAR_OVR_KEY
ADD_INV_
PAR
DAT_INV_PAR
R/WP-5h
R/WP-2h
R/WP-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -
n
= value after reset
Table 5-42. Parity Override Register (FPAR_OVR) Field Descriptions
Bit
Field
Value
Description
31-17
Reserved
0
Reserved
16
BNK_INV_PAR
Buffer Invert Parity
When this value is 1 and PAR_OVR_KEY is 101 then the current system parity signal
SYS_ODD_PARITY is inverted when doing bank parity calculations. This will generate parity errors
and cause interrupt signals to be generated. When 0, the SYS_ODD_PARITY value is used. This
bit is only implemented for parity configurations and is reserved for ECC devices.
15-12
BUS_PAR_DIS
Disable Bus Parity
When this value is 1010, the address bus parity error and buffer parity error are disabled and no
checking is done and no events are generated. Any other value will enable the parity checking on
the Address bus and read data bus. The read data parity is never disabled from this module.
11-9
PAR_OVR_KEY
When this value is 101, the selected ADD_INV_PAR and DAT_INV_PAR fields will become active.
Any other value will cause the module to use the global system parity bit in the system register
DEVCR1.
8
ADD_INV_PAR
Address Odd Parity
This bit is active only when PAR_OVR_KEY = 101. When ADD_INV_PAR is 1, the incoming
address bus will invert the system signal SYS_ODD_PARITY for parity calculations. This will cause
parity errors and generate interrupt error signals. When 0, it will use the SYS_ODD_PARITY value.
This bit is set to the SYS_ODD_PAR signal value on reset.
7-0
DAT_INV_PAR
Data Odd Parity
This byte is active only when PAR_OVR_KEY = 101. When a DATA_INV_PAR bit is 1, the output
read data will invert the system signal SYS_ODD_PARITY for parity calculations. This will cause
parity errors and generate interrupt signals. When 0, it will use the SYS_ODD_PARITY value. This
byte can support up to a 64 bit data bus but when the device has a 32 bit bus, bits 7:4 are
reserved.
Bit 0 affects read bus bits 7:0, Bit 1 affects read bus bits 15:8 and so on. Each active bit of this field
is set to the SYS_ODD_PAR signal value on reset.
The DAT_INV_PAR is used in the parity for the pipeline buffer logic and for the read data bus to the
CPU.
When the ECC logic is in the CPU (CONF_TYPE = 5) and SIL3 is active, this field becomes the
ECC corrupting value for SIL3 diagnostic mode 7. (Starting with version 1.0.0.0)
In diagnostic mode 7 the FPAR_OVR should be set to 00005Axxh to allow writes to the
DAT_INV_PAR field. This field should be written before entering diagnostic mode 7.
