Control and Status Registers
314
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Tightly-Coupled RAM (TCRAM) Module
6.7.5 TCRAM Module Error Status Register (RAMERRSTATUS)
The RAMERRSTATUS register, shown in
and described in
, indicates the status of
the various error conditions monitored by the TCRAM Module.
Figure 6-7. TCRAM Module Error Status Register (RAMERRSTATUS) [offset = 10h]
31
16
Reserved
R-0
15
10
9
8
Reserved
WADDR_
PAR_ FAIL
RADDR_
PAR_ FAIL
R-0
R/W1CP-0
R/W1CP-0
7
6
5
4
3
2
1
0
Reserved
DERR
ADDR_COMP_
LOGIC_FAIL
Reserved
ADDR_DEC_
FAIL
Reserved
SERR
R-0
R/W1CP-0
R/W1CP-0
R-0
R/W1CP-0
R-0
R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -
n
= value after reset
Table 6-6. TCRAM Module Error Status Register (RAMERRSTATUS) Field Descriptions
Bit
Field
Value
Description
31-10
Reserved
0
Read returns 0. Writes have no effect.
9
WADDR_PAR_FAIL
This bit indicates a Write Address Parity Failure. This bit must be cleared by writing 1 to it
in order to enable the capture of parity error address for subsequent failures. This bit must
be in a cleared state for generation of any new parity error interrupt.
8
RADDR_PAR_FAIL
This bit indicates a Read Address Parity Failure. This bit must be cleared by writing 1 to it
in order to enable the capture of parity error address for subsequent failures. This bit must
be in a cleared state for generation of any new parity error interrupt.
7-6
Reserved
0
Read returns 0. Writes have no effect.
5
DERR
This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic.
4
ADDR_COMP_LOGIC_FAIL
Address decode logic element failed. This bit indicates that the redundant address decode
logic test scheme has detected that a compare element has malfunctioned during the
testing of the logic. This bit has to be cleared by writing 1 to it in order to enable the
capture of uncorrectable error address for subsequent failures. This bit has to be in a
cleared state for generation of a new uncorrectable error interrupt. This bit only gets set in
the test mode, and has no relevance in functional mode.
3
Reserved
0
Read returns 0. Writes have no effect.
2
ADDR_DEC_FAIL
Address decode failed. This bit indicates that an address error interrupt was generated by
the redundant address decode and compare logic due to a functional failure. This bit must
be cleared by writing 1 to it in order to enable the capture of uncorrectable error address
for subsequent failures. This bit has to be in a cleared state for generation of a new
address error interrupt.
1
Reserved
0
Read returns 0. Writes have no effect.
0
SERR
Single Error Status. This bit indicates that the single-bit error threshold has been reached.
This bit is set even if the single-bit error threshold interrupt is disabled. This bit must be
cleared by writing 1 to it in order to clear the interrupt request and to enable subsequent
single-bit error interrupt generation.
