Module Operation
478
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Cyclic Redundancy Check (CRC) Controller Module
14.2.5 CRC Value Register
Associated with each channel there is a CRC Value Register. The CRC Value Register stores the pre-
determined CRC value. After one sector of data patterns is compressed by PSA Signature Register, CRC
Controller can automatically compare the resulting signature stored at the PSA Sector Signature Register
with the pre-determined value stored at the CRC Value Register if AUTO mode is enabled. If the signature
verification fails, CRC Controller can be enabled to generate an CRC fail interrupt. When the channel is
set up for Semi-CPU mode, CRC controller first generates a compression complete interrupt to CPU.
Upon servicing the interrupt, CPU will then read the PSA Sector Signature Register and then read the
corresponding CRC value stored at another location and compare them. CPU should not read from the
CRC Value Register during Semi-CPU or Full-CPU mode because the CRC Value Register is not updated
during these two modes.
In AUTO mode, for first sector’s signature, DMA request is generated when mode is programmed to
AUTO. For subsequent sectors, DMA request is generated after each sector is compressed. Responding
to the DMA request, DMA controller reloads the CRC Value Register for the next sector of memory system
to be checked.
When CRC Value Register is updated with a new CRC value, an internal flag is set to indicate that CRC
Value Register contains the most current value. This flag is cleared when CRC comparison is performed.
Each time at the end of the final data pattern compression of a sector, CRC Controller first checks to see
if the corresponding CRC Value Register has the most current CRC value stored in it by polling the flag. If
the flag is set then the CRC comparison can be performed. If the flag is not set then it means the CRC
Value Register contains stale information. A CRC underrun interrupt is generated. When an underrun
condition is detected, signature verification is not performed.
CRC Controller supports doubleword, word, half word and byte access to the CRC Value Register. As
noted before comparison between PSA Sector Signature Register and CRC Value Register during AUTO
mode is carried out in 64 bit.
14.2.6 Raw Data Register
The raw or un-compressed data written to the PSA Signature Register is also saved in the Raw Data
Register. This register is read only.
14.2.7 Example DMA Controller Setup
DMA controller needs to be setup properly in either AUTO or Semi-CPU mode as DMA controller is used
to transfer data patterns. Hardware or a combination of hardware and software DMA triggering are
supported.
14.2.7.1 AUTO Mode Using Hardware Timer Trigger
There are two DMA channels associated with each CRC channel when in AUTO mode. One DMA channel
is setup to transfer data patterns from the source memory to the PSA Signature Register. The second
DMA channel is setup to transfer the pre-determined signature to the CRC Value Register. The trigger
source for the first DMA channel can be either by hardware or by software. As illustrated in
a
timer can be used to trigger a DMA request to initiate transfer from the source memory system to PSA
Signature Register. In AUTO mode, CRC Controller also generates DMA request after one sector of data
patterns is compressed to initiate transfer of the next CRC value corresponding to the next sector of
memory. Thus a new CRC value is always updated in the CRC Value Register by DMA synchronized to
each sector of memory.
A block of memory system is usually divided into many sectors. All sectors are the same size. The sector
size is programmed in the CRC_PCOUNT_REGx and the number of sectors in one block is programmed
in the CRC_SCOUNT_REGx of the respective channel. CRC_PCOUNT_REGx multiplies
CRC_SCOUNT_REGx and multiplies transfer size of each data pattern should give the total block size in
number of bytes.
