USB Device Controller
1608
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
After completion of the data stage, a status stage IN transaction occurs. The USB module provides
handshaking to the USB host based on the endpoint 0 handshaking control bit STAT_FLG.FIFO_EN. The
CPU can delay signaling completion of the control write transfer by forcing NAK handshaking to the host
during the status stage (by holding STAT_FLG.FIFO_EN 0), or causing ACK handshaking by setting the
CTRL.SET_FIFO_EN bit with an empty endpoint 0 FIFO. An endpoint 0 TX general USB interrupt is sent
to the CPU at completion of the status stage.
After a SET_CONFIGURATION request, the device moves in addressed or configured state as soon as
the CPU sets the SYSCON2.DEV_CFG or SYSCON2.CLR_CFG bits.
29.3.7.3.1 Specific CPU Required Actions
If the device receives a valid set endpoint halt feature request, it must set the appropriate
CTRL.SET_HALT control bit.
If the device receives a valid CLEAR_ENDPOINT halt feature request, it must set the appropriate
CTRL.RESET_EP bit to clear the halt condition, FIFO flags, and reset data PID to DATA0 for the
endpoint. If the specified endpoint number is 0, the CPU has only to set CTRL.CLR_HALT bit to clear the
halt condition.
If the device receives a valid SET_CONFIGURATION request, it must reset all endpoints by setting the
CTRL.RESET_EP control bits, set the SYSCON1.SELF_PWR bit to the appropriate value, and then set
halt conditions for endpoints not used by the default interface set for the configuration. If the device was
addressed when the SET_CONFIGURATION was received, the CPU must write 1 to the
SYSCON2.DEV_CFG bit to allow the device to move into the configured state (DEVSTAT.CFG bit set). If
the device was configured when the SET_CONFIGURATION was received, and the new configuration
value is 0, the CPU must write 1 to the SYSCON2.CLR_CFG bit to allow the device to move back into the
addressed state (DEVSTAT.CFG bit cleared).
If the device receives a valid set interface request, it must reset all endpoints used by the interface set, by
setting CTRL.RESET_EP control bits, and then set halt conditions for endpoints not used by this interface.
Other CPU required actions are specific to the request and not detailed in this document.
29.3.7.3.2 Non-Autodecoded Control Write Transfer Handshaking
Setup stage transactions that are valid are signaled ACK. Transactions with invalid setup stage token or
data packets are ignored and receive no handshake packet from the USB module, and there is no
interrupt generated.
Data stage handshaking for non-autodecoded control write transfers is dependent on the endpoint 0
STAT_FLG.FIFO_EN, STAT_FLG.EP_HALTED, and SYSCON2.STALL_CMD bits. The CPU can delay
completion of any transaction of the data stage by signaling NAK (via CTRL.SET_FIFO_EN bit not set).
The USB specification requires that once STALL is signaled in a control transfer, it must be signaled on
that endpoint until the next setup token is received. Either the SYSCON2.STALL_CMD or the
CTRL.SET_HALT (reflected in the STAT_FLG.EP_HALTED register bit) register bits provide this
functionality. STAT_FLG.EP_HALTED does not reflect the forced STALL caused by
SYSCON2.STALL_CMD; it retains its previous value.
Status stage handshaking is controlled by the endpoint 0 STAT_FLG.FIFO_EN and
SYSCON2.STALL_CMD bits. Successful completion of a non-autodecoded control write transfer is
indicated by the USB device controller module returning a zero length data payload for the data phase of
the status stage and an ACK handshake from the host for the handshake phase of the status stage.
Although NAK handshaking can be used to indicate delays in completion of the requested control write,
the USB host can choose to abort the control write after some number of NAKs.
29.3.7.3.3 Non-Autodecoded Control Write Transfer Error Conditions
If an error occurs while dealing with the control write, which the CPU cannot deal with itself, it must signal
STALL to the USB host for all subsequent transactions until a new setup token to endpoint 0 occurs. This
is true for both data stage and status stage transactions. This is most conveniently done by setting
endpoint 0 SYSCON2.STALL_CMD bit, which causes stalling of all the remaining transactions of all
remaining stages of a non-autodecoded control transfer, up to the reception of the next valid SETUP
command.
