Operational Information
1385
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Inter-Integrated Circuit (I2C) Module
27.5.2 DMA Controller Events
The I2C module has two events that use the DMA controller to synchronously read received data
(I2CREVNT) from I2CDRR, and synchronously write data (I2CWEVNT) to the transmit buffer, I2CDXR.
The read and write events have the same timing as I2CRRDY (I2CRINT) and I2CXRDY (I2CXINT),
respectively.
The CPU or the DMA controller reads the received data from I2CDRR and writes the data to be
transmitted to I2CDXR. The RXRDY bit is automatically cleared when the DMA controller reads the
I2CDRR register, and the TXRDY bit is automatically cleared when the DMA controller writes to the
I2CDXR register.
Data written to I2CDXR is copied to I2CXSR and shifted out from the SDA pin when the I2C module is
configured as a transmitter. When the I2C module is configured as a receiver, received data is shifted into
ICRSR and copied to I2CDRR, which can be read by the CPU or the DMA controller.
A transmit event (I2CWEVNT) is generated after a START condition in master transmitter mode. This
ensures that the DMA gets an event even if no slave returns an ACK to the slave address following the
START condition.
NOTE:
Unexpected DMA transmit and receive event
An unexpected DMA transmit event (ICXEVT) and a DMA receive event (ICXRDY) are
generated in 10-bit, master transmit, repeat mode. This event occurs soon after the start
condition but before the first bit of the address is transmitted. In this event, no DMA activity
should be initiated without the slave ACK being received.
27.5.3 I2C Enable/Disable
The I2C module can be enabled or disabled with the I2C reset enable bit (IRS) in the I2C module register
(I2CMDR). This occurs in one of two ways:
•
Write 0 to the I2C reset bit (IRS) in I2CMDR. All status bits are forced to the default values and the I2C
mode remains disabled until IRS is changed to 1. The SDA and SCL pins are in the high impedance
state.
•
Initiate a device reset by driving the PORRST pin low. The entire device is reset and is held in the
reset state until the pin is released and is driven high. When PORRST is released, all I2C module
registers are reset to their default values. The IRS bit is forced to 0, which resets the I2C module. The
I2C module stays in the reset state until a 1 is written to the IRS bit.
IRS must be 0 while the I2C module is being configured. Forcing IRS to 0 can be used to save power and
also clear error conditions.
27.5.4 General Purpose I/O
Both of the I2C pins can be programmed to be general-purpose I/O pins via the I2C pin control registers
(I2CPFNC, I2CDIR, I2CDOUT, and I2CDIN).
When the I2C module is not used, the I2C pins may be programmed to be either general purpose input or
general-purpose output pins. This function is controlled in the I2CDIR and I2CPFNC registers. Note that
each pin can be programmed to be either an I2C pin or a GIO pin.
If the I2C function is to be used, the application software must ensure that each pin is configured as an
I2C pin and not a GIO pin, or else unexpected behavior may result.
