Texas Instruments RM48 series, Technical Reference Manual

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System and Peripheral Control Registers
133 SPNU503C – March 2018
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Architecture
2.5.1.13 Clock Domain Disable Register (CDDIS)
The CDDIS register, shown in Figure 2-18 and described in Table 2-32 , controls the state of the clock
domains.
NOTE: All the clock domains are enabled on wakeup.
The application should guarantee that when HCLK and VCLK_sys are turned off through the
HCLKOFF bit, the GCLK domain is also turned off.
The register bits in CDDIS are designated as high-integrity bits and have been implemented
with error-correcting logic such that each bit, although read and written as a single bit, is
actually a multi-bit key with error correction capability. As such, single-bit flips within the “key”
can be corrected allowing protection of the system as a whole. An error detected is signaled
to the ESM module.
Figure 2-18. Clock Domain Disable Register (CDDIS) [offset = 3Ch]
31 16
Reserved
R-0
15 12 11 10 9 8
Reserved VCLKA4OFF VCLKA3OFF Reserved VCLK3OFF
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 6 5 4 3 2 1 0
Reserved RTICLK1OFF Reserved VCLKA1OFF VCLK2OFF VCLKPOFF HCLKOFF GCLKOFF
R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; R = Read only; WP = Write in privileged mode only; - n = value after reset
Table 2-32. Clock Domain Disable Register (CDDIS) Field Descriptions
Bit Field Value Description
31-12 Reserved 0 Reads return 0. Writes have no effect.
11-10 VCLKA[4-3]OFF VCLKA[4-3] domain off.
0 The VCLKA[4-3] domain is enabled.
1 The VCLKA[4-3] domain is disabled.
9 Reserved 0-1 Reads return 0 or 1 and privilege mode writes allowed.
8 VCLK3OFF VCLK3 domain off.
0 The VCLK3 domain is enabled.
1 The VCLK3 domain is disabled.
7 Reserved 0-1 Reads return 0 or 1 and privilege mode writes allowed.
6 RTICLK1OFF RTICLK1 domain off.
0 The RTICLK1 domain is enabled.
1 The RTICLK1 domain is disabled.
5 Reserved 0-1 Reads return 0 or 1 and privilege mode writes allowed.
4 VCLKA1OFF VCLKA1 domain off.
0 The VCLKA1 domain is enabled.
1 The VCLKA1 domain is disabled.
3 VCLK2OFF VCLK2 domain off.
0 The VCLK2 domain is enabled.
1 The VCLK2 domain is disabled.
2 VCLKPOFF VCLK_periph domain off.
0 The VCLK_periph domain is enabled.
1 The VCLK_periph domain is disabled.