USB Device Controller
1599
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
29.3.4.1.2 Non-Acknowledged Transactions (NAK)
For the case in which the CPU is not ready to provide transmit data for transactions to an IN endpoint, the
core provides a NAK handshake to the host for any USB IN transaction to that endpoint . Readiness to
transmit data is signaled via the endpoint STAT_FLG.FIFO_EN bit; when 1 it indicates that data in the TX
FIFO can be sent to the USB host. When the endpoint STAT_FLG.FIFO_EN bit is 0 and an IN transaction
to the endpoint occurs, NAK handshake is sent, indicating that the CPU is not ready to handle the request.
If SYSCON1.NAK_EN bit is cleared, when the NAK handshake is sent in the data packet portion of the
transaction to the IN endpoint, STAT_FLG is not updated and no endpoint-specific interrupt to the CPU is
generated. If the SYSCON1.NAK_EN bit is set, when the NAK handshake is sent in the data packet
portion of the transaction to the IN endpoint, the STAT_FLG.NAK bit is set and an endpoint-specific
interrupt to the CPU is generated.
In response to the endpoint interrupt, the CPU must read the EPN_STAT register to identify the endpoint
causing the interrupt, and then write a 1 to the interrupt bit to clear it. The CPU must then set
EP_NUM.EP_NUM to the endpoint number, EP_NUM.EP_DIR to 1 (to signal an IN endpoint), and
EP_NUM.EP_SEL to 1, and then read the endpoint status from STAT_FLG. STAT_FLG.NAK is set to
indicate that the endpoint sent a NAK handshake to the USB host. If the CPU has data to transmit to the
USB host, it must fill the TX FIFO following the process indicated above. The CPU must then clear the
EP_NUM.EP_SEL bit. That clears the STAT_FLG.NAK bit for this endpoint to allow the next transaction
status to be written into the STAT_FLG register. Signaling NAK does not cause the endpoint TX FIFO to
be cleared (because the CPU still retains control of the FIFO).
Signaling NAK handshake for several endpoint transactions in a row can cause the PC host to discard the
transaction, so NAK is not necessarily a good mechanism in cases where the CPU is not able to service a
request for long periods of time.
29.3.4.2 Non-Isochronous IN Transaction Error Conditions
29.3.4.2.1 STALLed Transactions
The USB module sends a STALL handshake to the USB host during the data phase of the transaction to
the IN endpoint either if the endpoint STAT_FLG.EP_HALTED flag is set, or if a request error occurs
(control transaction only). A USB STALL handshake indicates that the device endpoint is in a condition in
which it is not able to transfer data and instructs the USB host not to retry the transaction. The device
typically requires intervention via some other mechanism to clear the condition, usually a control transfer
via endpoint 0. The CPU can set the endpoint EP_HALTED bit by selecting the endpoint by writing the
appropriate value in EP_NUM register, and then setting the endpoint CTRL.Set_HALT bit, and clear it by
selecting the endpoint, and then setting the endpoint CTRL.Clr_HALT bit. When the endpoint
EP_HALTED bit is set, the endpoint signals STALL for its IN transactions until the HALT condition is
cleared. When the STALL handshake is sent in response to a transaction to the endpoint, the
STAT_FLG.STALL bit is set, and an endpoint-specific interrupt to the CPU is generated.
In response to the endpoint interrupt, the CPU must read the EPN_STAT register to identify the endpoint
causing the interrupt, and then write a 1 to the interrupt bit to clear it. The CPU must then set
EP_NUM.EP_NUM to the endpoint number, EP_NUM.EP_DIR to 1 (to signal an IN endpoint), and
EP_NUM.EP_SEL to 1, and then read the endpoint status from STAT_FLG. STAT_FLG.STALL is set to
indicate that the endpoint sent a STALL handshake to the USB host. The CPU must then clear
EP_NUM.EP_SEL bit. This clears the STAT_FLG.STALL bit for this endpoint and allows the next
transaction status to be written into the STAT_FLG register.
Except for control endpoint 0, separate endpoint halt bits are defined for each direction; so for a given
endpoint number, the TX can be halted when the RX is not.
