Module Operation
485
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Cyclic Redundancy Check (CRC) Controller Module
14.2.11.1 Data Capture Mode used in Conjunction with Data Trace
Data capture mode is especially useful when it is used in conjunction when data trace for channel 1 is
enabled (CRC_CTRL2.CH1_TRACEEN = 1). The seed value can be planted in PSA Signature Register
during data capture mode by writing a seed value into PSA Signature Register. The data trace enable bit
is then set to snoop and compress any read transaction on DAHB bus. When trace enable bit is set,
CRC_CTRL2.CH1_MODE is automatically reset to 0 (data capture mode). To change from one mode to
another mode in the middle of an on-going mode, perform the following steps:
1. Assert software reset for the respective channel.
2. Change from the current active mode to Data Capture mode (CRC_CTRL2.CH1_MODE = 0).
3. Change from Data Capture mode to the new mode.
4. Release software reset.
14.2.12 Power Down Mode
CRC module can be put into power down mode when the power down control bit PWDN is set. The
module wakes up when the PWDN bit is cleared. When CRC controller is in power down mode, no data
tracing alone will happen. However, if CRC registers are accessed then data trace happens from channel
1.
14.2.13 Emulation
A read access from a register in functional mode can sometimes trigger a certain internal event to follow.
For example, reading an interrupt offset register triggers an event to clear the corresponding interrupt
status flag. During emulation when SUSPEND signal is high, a read access from any register should only
return the register contents to the bus and should not trigger or mask any event as it would have in
functional mode. This is to prevent debugger from reading the interrupt offset register during refreshing
screen and cause the corresponding interrupt status flag to get cleared. Timeout counters are stopped to
generate timeout interrupts in emulation mode. No Peripheral Master bus error should be generated if
reading from the unimplemented locations. When channel 1 is placed under data trace, the PSA Signature
Register does not compress any data read on CPU data bus when suspend is active.
14.2.14 Peripheral Bus Interface
CRC is a Peripheral slave module. The register interface is similar to other peripheral modules. CRC
supports following features:
•
Different sizes of burst operation.
•
Aligned and unaligned accesses.
•
Abort is generated for any illegal address accesses.
