14
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Contents
19.11.1
ADC Reset Control Register (ADRSTCR)
.................................................................
19.11.2
ADC Operating Mode Control Register (ADOPMODECR)
..............................................
19.11.3
ADC Clock Control Register (ADCLOCKCR)
..............................................................
19.11.4
ADC Calibration Mode Control Register (ADCALCR)
....................................................
19.11.5
ADC Event Group Operating Mode Control Register (ADEVMODECR)
..............................
19.11.6
ADC Group1 Operating Mode Control Register (ADG1MODECR)
.....................................
19.11.7
ADC Group2 Operating Mode Control Register (ADG2MODECR)
.....................................
19.11.8
ADC Event Group Trigger Source Select Register (ADEVSRC)
.......................................
19.11.9
ADC Group1 Trigger Source Select Register (ADG1SRC)
..............................................
19.11.10
ADC Group2 Trigger Source Select Register (ADG2SRC)
............................................
19.11.11
ADC Event Interrupt Enable Control Register (ADEVINTENA)
........................................
19.11.12
ADC Group1 Interrupt Enable Control Register (ADG1INTENA)
.....................................
19.11.13
ADC Group2 Interrupt Enable Control Register (ADG2INTENA)
.....................................
19.11.14
ADC Event Group Interrupt Flag Register (ADEVINTFLG)
............................................
19.11.15
ADC Group1 Interrupt Flag Register (ADG1INTFLG)
..................................................
19.11.16
ADC Group2 Interrupt Flag Register (ADG2INTFLG)
..................................................
19.11.17
ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR)
........................
19.11.18
ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR)
..............................
19.11.19
ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR)
..............................
19.11.20
ADC Event Group DMA Control Register (ADEVDMACR)
............................................
19.11.21
ADC Group1 DMA Control Register (ADG1DMACR)
...................................................
19.11.22
ADC Group2 DMA Control Register (ADG2DMACR)
...................................................
19.11.23
ADC Results Memory Configuration Register (ADBNDCR)
...........................................
19.11.24
ADC Results Memory Size Configuration Register (ADBNDEND)
....................................
19.11.25
ADC Event Group Sampling Time Configuration Register (ADEVSAMP)
...........................
19.11.26
ADC Group1 Sampling Time Configuration Register (ADG1SAMP)
..................................
19.11.27
ADC Group2 Sampling Time Configuration Register (ADG2SAMP)
..................................
19.11.28
ADC Event Group Status Register (ADEVSR)
..........................................................
19.11.29
ADC Group1 Status Register (ADG1SR)
.................................................................
19.11.30
ADC Group2 Status Register (ADG2SR)
.................................................................
19.11.31
ADC Event Group Channel Select Register (ADEVSEL)
..............................................
19.11.32
ADC Group1 Channel Select Register (ADG1SEL)
.....................................................
19.11.33
ADC Group2 Channel Select Register (ADG2SEL)
.....................................................
19.11.34
ADC Calibration and Error Offset Correction Register (ADCALR)
....................................
19.11.35
ADC State Machine Status Register (ADSMSTATE)
...................................................
19.11.36
ADC Channel Last Conversion Value Register (ADLASTCONV)
.....................................
19.11.37
ADC Event Group Results' FIFO Register (ADEVBUFFER)
...........................................
19.11.38
ADC Group1 Results FIFO Register (ADG1BUFFER)
.................................................
19.11.39
ADC Group2 Results FIFO Register (ADG2BUFFER)
.................................................
19.11.40
ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER)
........................
19.11.41
ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)
...............................
19.11.42
ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)
...............................
19.11.43
ADC ADEVT Pin Direction Control Register (ADEVTDIR)
.............................................
19.11.44
ADC ADEVT Pin Output Value Control Register (ADEVTOUT)
.......................................
19.11.45
ADC ADEVT Pin Input Value Register (ADEVTIN)
.....................................................
19.11.46
ADC ADEVT Pin Set Register (ADEVTSET)
............................................................
19.11.47
ADC ADEVT Pin Clear Register (ADEVTCLR)
..........................................................
19.11.48
ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR)
.........................................
19.11.49
ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS)
........................................
19.11.50
ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL)
.........................................
19.11.51
ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN)
.................
19.11.52
ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN)
.......................
19.11.53
ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)
.......................