Texas Instruments RM48 series, Technical Reference Manual

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ADC Control Registers
765 SPNU503C – March 2018
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Analog To Digital Converter (ADC) Module
19.11.38 ADC Group1 Results FIFO Register (ADG1BUFFER)
ADC Group1 Results FIFO Register (ADG1BUFFER) is shown in Figure 19-60 and Figure 19-61 ,
described in Table 19-43 . As shown, the format of the data read from the ADG1BUFFER locations is
different based on whether the ADC module is configured to be a 12-bit or a 10-bit ADC module.
Figure 19-60. 12-bit ADC Group1 Results FIFO Register (ADG1BUFFER)
[offset = B0h-CFh]
31 30 21 20 16
G1_EMPTY Reserved G1_CHID
R-1 R-0 R-0
15 12 11 0
Reserved G1_DR
R-0 R-U
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset; -U = value after reset is unknown
Figure 19-61. 10-bit ADC Group1 Results' FIFO Register (ADG1BUFFER)
[offset = B0h-CFh]
31 16
Reserved
R-0
15 14 10 9 0
G1_EMPTY G1_CHID G1_DR
R-1 R-0 R-U
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset; -U = value after reset is unknown
Table 19-43. ADC Group1 Results FIFO Register (ADG1BUFFER) Field Descriptions
Field Value Description
Reserved 0 Reads return zeros, writes have no effect.
G1_EMPTY Group1 FIFO Empty. This bit is applicable only when the "read from FIFO" mode is used for reading the
Group1 conversion results.
Any operation mode read:
0 The data in the G1_DR field of this buffer is valid.
1 The data in the G1_DR field of this buffer is not valid and there are no valid data in the Group1 results
memory.
G1_CHID Group1 Channel Id. These bits are also applicable only when the "read from FIFO" mode is used for
reading the Group1 conversion results.
Any operation mode read:
0 The conversion result in the G1_DR field of this buffer is from the ADC input channel 0, or the channel id
mode is disabled in the Group1 operating mode control register (ADG1MODECR).
1h-1Fh The conversion result in the G1_DR field of this buffer is from the ADC input channel number denoted by
the G1_CHID field.
G1_DR Group1 Digital Conversion Result.
The Group1 results’ FIFO location is aliased eight times, so that any word-aligned read from the address
range 0xB0 to 0xCF results in one conversion result to be read from the Group1 results’ memory. This
allows the ARM LDMIA instruction to read out up to 8 conversion results from the Group1 results’ memory
with just one instruction.