Introduction
616
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
17.1 Introduction
17.1.1 Purpose of the Peripheral
This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories utilizing a 16-bit
data bus. The purpose of this EMIF is to provide a means for the CPU to connect to a variety of external
devices including:
•
Single data rate (SDR) SDRAM
•
Asynchronous devices including NOR Flash and SRAM
The most common use for the EMIF is to interface with both a flash device and an SDRAM device
simultaneously.
contains an example of operating the EMIF in this configuration.
17.1.2 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external SDR
SDRAM and asynchronous devices.
17.1.2.1 Asynchronous Memory Support
EMIF supports asynchronous:
•
SRAM memories
•
NOR Flash memories
The EMIF data bus width is up to 16 bits and there are up to 22 address lines. There is an external wait
input that allows slower asynchronous memories to extend the memory access. The EMIF module
supports up to 3 chip selects (EMIF_nCS[4:2]). Each chip select has the following individually
programmable attributes:
•
Data Bus Width
•
Read cycle timings: setup, hold, strobe
•
Write cycle timings: setup, hold, strobe
•
Bus turn-around time
•
Extended Wait Option with Programmable Timeout
•
Select Strobe option
17.1.2.2 Synchronous DRAM Memory Support
The EMIF module supports 16-bit SDRAM in addition to the asynchronous memories listed in
. It has a single SDRAM chip select (EMIF_nCS[0]). SDRAM configurations that are
supported are:
•
One, Two and Four Bank SDRAM devices
•
Devices with Eight, Nine, Ten, and Eleven Column Address
•
CAS Latency of two or three clock cycles
•
16-bit Data Bus Width
•
3.3V LVCMOS Interface
Additionally, the EMIF supports placing the SDRAM in Self-Refresh and Powerdown modes. Self-refresh
mode allows the SDRAM to be put in a low-power state while still retaining memory contents; since the
SDRAM will continue to refresh itself even without clocks from the microcontroller. Powerdown mode
achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if
data retention is required.
Note that the EMIF module does not support Mobile SDRAM devices.
