Example Configuration
662
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
17.4 Example Configuration
This section presents an example of interfacing the EMIF to both an SDR SDRAM device and an
asynchronous flash device.
17.4.1 Hardware Interface
shows the hardware interface between the EMIF, a Samsung K4S641632H-TC(L)70 64Mb
SDRAM device, and two SHARP LH28F800BJE-PTTL90 8Mb Flash memory. The connection between
the EMIF and the SDRAM is straightforward, but the connection between the EMIF and the flash deserves
a detailed look.
The address inputs for the flash are provided by three sources. The A[18:0] address inputs are provided
by a combination of the EMIF_A and EMIF_BA pins according to
. RD/nBY signal from
one flash is connected to EMIF_nWAIT pin of EMIF.
Finally, this example configuration connects the EMIF_nWE pin to the nWE input of the flash and operates
the EMIF in Select Strobe Mode.
17.4.2 Software Configuration
The following sections describe how to configure the EMIF registers and bit fields to interface the EMIF
with the Samsung K4S641632H-TC(L)70 SDRAM and the SHARP LH28F800BJE-PTTL90 8Mb Flash
memory.
17.4.2.1 Configuring the SDRAM Interface
This section describes how to configure the EMIF to interface with the Samsung K4S641632H-TC(L)70
SDRAM with a clock frequency of f
EMIF_CLK
= 100 MHz. Procedure A described in
is
followed which assumes that the SDRAM power-up timing constraint were met during the SDRAM Auto-
Initialization sequence after Reset.
17.4.2.1.1 PLL Programming for the EMIF to K4S641632H-TC(L)70 Interface
The device global clock module (GCM) should first be programmed to select the desired EMIF_CLK
frequency. Before doing this, the SDRAM should be placed in Self-Refresh Mode by setting the SR bit in
the SDRAM configuration register (SDCR). The SR bit should be set using a byte-write to the upper byte
of the SDCR to avoid triggering the SDRAM Initialization Sequence. The EMIF_CLK frequency can now
be configured to the desired value by selecting the appropriate clock source for the VCLK3 domain. Once
the VCLK3 domain frequency has been configured, remove the SDRAM from Self-Refresh by clearing the
SR bit in SDCR, again with a byte-write.
Table 17-37. SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface
Field
Value
Purpose
SR
1 then 0
To place the EMIF into the self refresh state
