Basic Features and Usage of the ADC
700
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Analog To Digital Converter (ADC) Module
The application can identify the address ranges for each of the three memory regions for the three
conversion groups after performing the segmentation as described in
. It is up to the
application to read the desired results from the three conversion groups. The formats of the conversion
results when reading from RAM directly are shown in the following figures.
Figure 19-7. Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC
ADC
RAM
address
Reserved
channel id [4]
channel id [3-0]
12-bit conversion result
Figure 19-8. Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC
ADC
RAM
address
Reserved
Rsvd
channel id [4-0]
10-bit conversion result
Note that there is no EMPTY field to protect the application from reading data that has been previously
read.
Each group does have a separate register which holds the address in the group’s result memory where
the ADC will write the next conversion result. These are the ADEVRAMWRADDR, ADG1RAMWRADDR,
and ADG2RAMWRADDR registers. The application can use this information to calculate how many valid
conversion results are available to be read.
Benefit of reading conversion results directly from ADC RAM:
The application does not have to read out conversion results sequentially as in the case of reading from a
FIFO. As a result, the application can selectively read the conversion results for any particular input
channel of interest without having to read other channels’ conversion results.
19.3.9.3 Example
Suppose that channels 0, 1, and 2 are selected for conversion in the Event Group, channels 4, 7, and 8
are selected for conversion in group 1, and channels 3, 5, and 6 are selected for conversion in group 2.
The conversion results will get stored in the three memory regions as shown in
Suppose that the CPU wants to read out the results for the Event Group from a FIFO queue. The CPU
needs to read from any address in the range ADEVBUFFER (offset 0x90 to 0xAF) multiple times, or do a
“load multiple” from this range of addresses. This will cause the ADC to return the results for channel 0,
then channel 1, then channel 2, then channel 0, and so on for each read access to this address range.
Now suppose that the application wants to read out the results for the group 1 from the RAM directly. The
conversion results for the group 1 are accessible starting from address ADC RAM Base A BNDA.
Also, it is known that the first result at this address is for the input channel 4, the next one is for input
channel 7, and so on. So the application can selectively read the conversion results for only one channel if
so desired.
