SCI/LIN Control Registers
1299
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
Table 25-19. SCI Flags Register (SCIFLR) Field Descriptions (continued)
Bit
Field
Value
Description
7
TOA3WUS
Timeout after three wakeup signals flag. This bit is effective in LIN mode only. This flag is set if
there is no synch break received after three wakeup signals and a period of 1.5 seconds has
passed. Such expiration time is used before issuing another round of wakeup signals. This bit is
cleared by the following:
• Setting of the SWnRST bit
• Setting of the RESET bit
• A system reset
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
See
for more information.
0
Read:
No timeout occurred after three wakeup signals.
Write:
Writing a 0 to this bit has no effect.
1
Read:
Timeout occurred after three wakeup signals and 1.5 seconds time.
Write:
The bit is cleared to 0.
6
TOAWUS
Timeout after wakeup signal flag. This bit is effective in LIN mode only. This bit is set if there is no
synch break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is
used before issuing another wakeup signal. This bit is cleared by the following:
• Setting the SWnRST bit
• Setting of the RESET bit
• A system reset occurring
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
See
for more information.
0
Read:
No timeout occurred after one wakeup signal (150 ms).
Write:
Writing a 0 to this bit has no effect.
1
Read:
Timeout occurred after one wakeup signal.
Write:
The bit is cleared to 0.
5
Reserved
0
Reads return 0. Writes have no effect.
4
TIMEOUT
LIN bus idle timeout flag. This bit is effective in LIN mode only. This bit is set earliest after at least
four seconds of bus inactivity. Bus inactivity is defined as no transactions between recessive and
dominant (and vice versa). This bit is cleared by the following:
• Setting the SWnRST bit
• Setting of the RESET bit
• A system reset occurring
• Writing a 1 to this bit
• Reading the corresponding interrupt offset in SCIINTVECT0/1
See
for more information.
0
Read:
No bus idle has been detected since this bit was last cleared.
Write:
Writing a 0 to this bit has no effect.
1
Read:
A LIN bus idle has been detected.
Write:
The bit is cleared to 0.
3
BUSY
Bus busy flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates
whether the receiver is in the process of receiving a frame. As soon as the receiver detects the
beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the
SCI/LIN clears the BUSY bit. If SET WAKEUP INT is set and power down is requested while this bit
is set, the SCI/LIN automatically prevents low-power mode from being entered and generates
wakeup interrupt. The BUSY bit is controlled directly by the SCI/LIN receiver, but this bit can also
be cleared by the following:
• Setting the SWnRST bit
• Setting of the RESET bit
• A system reset occurring
0
The receiver is not currently receiving a frame.
1
The receiver is currently receiving a frame.
