Texas Instruments RM48 series, Technical Reference Manual

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PLL Control Registers
387 SPNU503C – March 2018
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Oscillator and PLL
10.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)
This is observation register used to log counter value for CLKOUT counter inside PLL wrapper. This
register applies to PLL1, but does not apply to PLL2. The SSWPLL3 register is shown in
Figure 10-8 and
described in Table 10-8 .
Figure 10-8. SSW PLL BIST Control Register 3 (SSWPLL3) [offset = FF2Ch]
31 16
SSW_CLKOUT_COUNT
R-0
15 0
SSW_CLKOUT_COUNT
R-0
LEGEND: R = Read only; - n = value after reset
Table 10-8. SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions
Bit Field Value Description
31-0 SSW_CAPTURE_COUNT 0-FFFF FFFFh Value of CLKout count register. This counter increments based upon the PLL
output (prior to the R-divider).