Clock Source Selection for Counter0 and Counter1
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SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Dual-Clock Comparator (DCC) Module
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The DCC error interrupt service routine can then check the value of counter1 when the error was
generated. Suppose that the counter1 now reads 1044575. This means that counter1 has counted
1048575 - 1044575, or 4000 cycles within the 500µs measurement period. This means that the
average frequency of the HF LPO over this 500µs period was 4000 cycles / 500µs, or 8MHz.
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The application then needs to clear the ERROR status flag and restart the DCC module so that it is
ready for the next spot measurement.
If there is no error generated at the end of the sequence, then the DONE status flag is set and a DONE
interrupt is generated. The application must clear the DONE flag before restarting the DCC.
The conditions that cause a DCC error are identical between the continuous monitoring mode and the
single-shot measurement mode.
Error Conditions:
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that clock1 is faster than
expected, or clock0 is slower than expected. It includes the case when clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that
clock1 is slower than expected. It includes the case when clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application may then read out the counter values
to help determine what caused the error.
Freezing Counters when Counter1 Reaches Zero:
The DCC module also allows the counters to be frozen when the counter1 reaches zero. This allows
one of the clock sources for counter1 to be used as a reference for measuring one of the clock sources
for counter0. The error conditions are the same as those where (counter0=0 and valid0=0) define the
condition when the DCC counters are frozen. That is, an error is indicated if coutner0 and valid0
become zero while counter1 is still non-zero. In this case, however, the application would typically set
up the seed values such that the counter1 will become zero before counter0. Essentially the
measurement period is defined by the seed value of the counter1. Note that this is also an error
condition, and the interrupt service routine can use the measurement period and the actual cycles
counted by counter1 to determine the frequency of the clock0 signal.
11.3 Clock Source Selection for Counter0 and Counter1
Refer to the device datasheet to identify the available options for selecting the clock sources for both
counters of the DCC module. Some microcontrollers may include multiple instances of the DCC module.
This will also be identified in the device datasheet.
The selection of the clock sources for counter0 and coutner1 is done by a combination of the KEY, CNT0
CLKSRC, and CNT1 CLKSRC control fields of the CNT0CLKSRC and CNT1CLKSRC registers.
