Basic Features and Usage of the ADC
696
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Analog To Digital Converter (ADC) Module
19.3 Basic Features and Usage of the ADC
This section describes the usage of the basic features of the ADC module.
19.3.1 How to Select Between 12-bit and 10-bit Resolution
The 10_12_BIT field of the ADC Operating Mode Control Register (ADOPMODECR) configures the ADC
to be in 10-bit or 12-bit resolution mode.
•
If 10_12_BIT = 0, the module is in 10-bit resolution mode. This is the default mode of operation.
•
If 10_12_BIT = 1, the module is in 12-bit resolution mode.
19.3.2 How to Set Up the ADCLK Speed
The ADC sequencer generates the clock for the ADC core, ADCLK. The ADC core uses the ADCLK
signal for its timing. The ADCLK is generated by dividing down the input clock to the ADC module, which
is the VBUSP interface clock, VCLK. A 5-bit field (PS) in the ADC Clock Control Register (ADCLOCKCR)
is used to divide down the VCLK by 1 up to 32. The ADCLK valid frequency range is specified in the
device datasheet.
f
ADCLK
= f
VCLK
/ (PS + 1)
The maximum frequency for ADCLK is specified in the device datasheet.
19.3.3 How to Set Up the Input Channel Acquisition Time
The signal acquisition time for each group is separately configurable using the ADG1SAMP[11:0],
ADG2SAMP[11:0], and ADEVSAMP[11:0] registers.
The acquisition time is specified in terms of ADCLK cycles and ranges from a minimum of 2 ADCLK
cycles to a maximum of 4098 ADCLK cycles.
For example, Group1 acquisition time, t
ACQG1
= G1SAMP[11:0] + 2, in ADCLK cycles.
The minimum acquisition time is specified in the device datasheet. This time also depends on the
impedance of the circuit connected to the analog input channel being converted. See the
ADC Source
Impedance for Hercules™ ARM
®
Safety MCUs Application Report
).
19.3.4 How to Select an Input Channel for Conversion
The ADC module needs to be enabled first before selecting an input channel for conversion. The ADC
module can be enabled by setting the ADC EN bit in the ADC Operating Mode Control Register
(ADOPMODECR). Multiple input channels can be selected for conversion in each group. Only one input
channel is converted at a time. The channels to be converted are configured in one or more of the three
conversion groups’ channel selection registers. Channels to be converted in Group1 are configured in the
Group1 Channel-Select Register (ADG1SEL), those to be converted in Group2 are configured in the
Group2 Channel-Select Register (ADG2SEL), and those to be converted in the Event Group are
configured in the Event Group Channel-Select Register (ADEVSEL).
19.3.5 How to Select Between Single Conversion Sequence or Continuous Conversions
Each group has its own mode control register. The MODE field of these control registers allow the
application to select between a single conversion sequence or continuous conversion mode.
NOTE:
Selecting continuous conversion mode for all three groups
All three conversion groups cannot be configured to be in a continuous conversion mode. If
the application configures the group mode control registers to enable continuous conversion
mode for all three groups, then the Group2 will be automatically be configured to be in a
single conversion sequence mode.
