Introduction
97
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Architecture
Table 2-1. Definition of Terms (continued)
Acronym/Term
Full Form
Description
HTUx
High-end timer Transfer Unit
The HTU is a dedicated transfer unit for the New Enhanced High-End Timer
module. The HTU has a native interface to the N2HET RAM, and is used to
transfer data to / from the N2HET RAM from / to another region in the device
memory-map. There is one HTU per N2HET module, so that there are 2 HTU
modules on the device. The HTUx are bus masters in this device.
I2C
Inter-Integrated Circuit
controller
The I2C module is a multi-master communication module providing an interface
between the device and an I2C-compatible device via the I2C serial bus. The
I2C supports both 100 Kbps and 400 Kbps speeds.
LIN
Local Interconnect Network
controller
The LIN module supports the Local Interconnect standard revision 2.1 and can
be used as a UART in full-duplex mode using the standard Non-Return-to-Zero
(NRZ) format.
Lockstep
–
This is the mode of operation of the dual ARM Cortex-R4F CPUs. The outputs of
the two CPUs are compared on each CPU clock cycle. Any miscompare is
flagged as an error of the highest severity level.
MibSPIx
Multi-Buffered Serial
Peripheral Interface
The MibSPIx modules also support the standard SPI communication protocol.
The transfers are all grouped into transfer chunks called “transfer groups”. These
transfer groups are made up of one ore more buffers in the MibSPIx RAM. The
RAM is used to hold the control information and data to be transmitted, as well
as the status information and data that is received. There are three MibSPI
modules in this device.
N2HETx
New Enhanced High-End
Timer
The N2HET is an advanced intelligent timer that provides sophisticated timing
functions for real-time applications. The timer is software-controlled, using a
reduced instruction set, with a specialized timer micromachine and an attached
I/O port. The N2HET can be used for pulse width modulated outputs, capture or
compare inputs, or general-purpose I/O.
PCR
Peripheral Central Resource
controller
The PCR manages the accesses to the peripheral registers and peripheral
memories. It provides a global reset for all the peripherals. It also supports the
capability to selectively enable or disable the clock for each peripheral
individually. The PCR also manages the accesses to the system module
registers required to configure the device’s clocks, interrupts, and so on. The
system module registers also include status flags for indicating exception
conditions – resets, aborts, errors, interrupts.
POM
Parameter Overlay Module
The parameter overlay module redirects accesses to a programmable region in
flash memory (read-only) to a RAM memory, either on-chip or via the external
memory interface (EMIF). This allows a user to evaluate the impact of changing
values of constants stored in the flash memory without actually having to erase
and reprogram the flash. The POM is also a bus master in this device.
SCI
Serial Communication
Interface
The SCI module supports the standard UART in full-duplex mode using the
standard Non-Return-to-Zero (NRZ) format.
SCR1:
AHB BMM
AMBA High-Performance Bus
Matrix Module
The DMA, DMM, POM and DAP all act as masters on the AMBA High-
performance Bus (AHB). The BMM arbitrates between concurrent accesses by
these masters using a fixed priority scheme. The modules in descending order
of priority are POM —> DMA —> DMM —> DAP.
SCR2:
VBUSP SCR
VBUSP Switched Central
Resource Controller
The SCR2 arbitrates between concurrent accesses by the HTU1 and HTU2. A
round-robin priority scheme is used between the HTU1 and HTU2.
SCR3:
VBUSP SCR
VBUSP Switched Central
Resource Controller
The SCR3 arbitrates between concurrent accesses by the EMAC and another
module that is not available in this configuration of the device.
SCR4:
VBUSP SCR
VBUSP Switched Central
Resource Controller
The SCR4 is used to decode the accesses to the bus slaves for the EMAC and
EMIF modules. SCR4 is a bus slave in this device.
SPIx
Serial Peripheral Interface
The SPIx modules provide a clocked serial communication interface for reliable
communication between the device and other serial devices with the standard
SPI interface. There are two SPI modules on this device.
USB
Universal Serial Bus
This device provides several varieties of USB functionality, including:
• One full-speed USB device port compatible with the USB Specification
Revision 2.0 and USB Specification Revision 1.1
• Two USB host ports compatible with USB Specification Revision 2.0, which
is based on the OHCI Specification For USB Release 1.0
VBUSM SCR
VBUSM Switched Central
Resource Controller
This is the main device SCR. It arbitrates between the accesses from multiple
bus masters to the bus slaves using a round robin priority scheme.
