USB Device Controller
1609
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Universal Serial Bus (USB)
Error conditions are handled as for BULK/INTERRUPT transactions. If a packet is received corrupted, the
core ignores the transaction and no interrupt is asserted.
29.3.7.4 Non-Autodecoded Control Read Transfers
Non-autodecoded control read transfers include the GET_INTERFACE_STATUS,
GET_CONFIGURATION, GET_INTERFACE, GET_DESCRIPTOR, SYNCH_FRAME and class- or
vendor-specific control read transfers. Non-autodecoded control read transfers consist of three stages
(setup, data, and status).
The setup stage of a valid non-autodecoded control read transfer consists of one SETUP transaction from
USB host to USB device. At the end of the setup stage handshake, the USB module generates a CPU
general USB interrupt with the IRQ_SRC.SETUP flag set. The CPU must respond to this general USB
interrupt by setting the EP_NUM.SETUP_SEL bit, which clears the setup interrupt flag. The CPU must
then read 8 bytes from the setup FIFO via the DATA register, clear the EP_NUM.EP_SEL bit, and check
the IRQ_SRC.SETUP flag. If the IRQ_SRC.SETUP flag is set, the CPU must discard the setup data it has
just read and handle the new setup data packet following the same scheme. If the IRQ_SRC.SETUP flag
is cleared, the CPU code interprets this request information and then prepares data for the IN transaction
that follow. This includes placing the data being requested (or the first few bytes, if more than one FIFO
worth of data is being returned) into the endpoint 0 FIFO, and setting the CTRL.SET_FIFO_EN bit.
The data stage of a control read transfer consists of one or more IN transactions. Transaction
handshaking and interrupt generation as for non-isochronous, non-control IN endpoints applies; the CPU
can cause NAK, STALL, or ACK signaling for the data stage transactions. At endpoint 0 TX general USB
interrupts, CPU code must move more data to the endpoint 0 FIFO, until the last bytes of the requested
data have been provided. Although SETUP packets have a defined payload length, the USB host can
cancel the transaction at any time, without the status stage, and resend another SETUP command. The
CPU code must be able to operate correctly in this situation.
After completion of the data stage, a status stage OUT transaction occurs. The USB host sends a zero-
length data packet, and the CPU code must return its completion status for the control read standard
request via standard handshaking mechanisms.
NOTE:
In the case of returning exactly what the host requested and that request was a multiple of
the maximum packet size, no zero-length packet is required. A zero-length packet is required
only when the amount of data the device has to return is less than the amount requested by
the host and the amount returned is a multiple of the maximum packet size (source USB
forum).
29.3.7.4.1 Non-Autodecoded Control Read Transfer Handshaking
Handshaking for the setup stage of non-autodecoded control read transfers is forced by the USB module
to always be ACK, unless there is a data error in the packet, in which case the USB module ignores the
transaction. If the setup packet has a DATA1 PID instead of a DATA0 PID, the setup transaction is
ignored (error).
Data stage handshaking for non-autodecoded control read transfers is dependent on the endpoint 0
STAT_FLG.FIFO_EN, STAT_FLG.EP_HALTED, and SYSCON2.STALL_CMD bits. The handshaking
information is used during the data phase of the data stage transaction. The USB specification requires
that once STALL is signaled in a control transfer, it must be signaled until the next setup token is received.
The SYSCON2.STALL_CMD and CTRL.SET_HALT (reflected through the STAT_FLG.EP_HALTED
register bit) register bits provide this functionality. STAT_FLG.EP_HALTED does not reflect the forced
STALL caused by SYSCON2.STALL_CMD; it retains its previous value.
The status stage is controlled by the CTRL.FIFO_EN andSYSCON2.STALL_CMD bits.
Successful completion of non-autodecoded control read transfers is indicated by the host sending an OUT
token followed by an empty packet and the USB device controller responding with ACK. If the data packet
sent by the USB host during the status stage of a control read request is not empty, the OUT transaction
is accepted by the core, but OUT data is not put into the endpoint 0 RX FIFO. If the status packet has a
DATA0 PID instead of a DATA1 PID, a STALLed is returned by the core and an interrupt is asserted.
